Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - Op-amp Multi-purpose SOIC 8

LMC6572, LMC6574

www.ti.com

SNOS707D –DECEMBER 1996–REVISED MARCH 2013

LMC6572/LMC6574 Dual and Quad Low Voltage (2.7V and 3V) Operational Amplifier

Check for Samples: LMC6572, LMC6574

FEATURES

DESCRIPTION

Low voltage operation and low power dissipation

• (Typical Unless Otherwise Noted)

make the LMC6574/2 ideal for battery-powered

• Guaranteed 2.7V and 3V Performance

systems.

• Rail-to-Rail Output Swing (Within 5 mV of

3V amplifier performance is backed by 2.7V

Supply Rail, 100 kΩ Load)

guarantees to ensure operation throughout battery

• Ultra-Low Supply Current: 40 μA/Amplifier

lifetime. These guarantees also enable analog circuits

to operate from the same 3.3V supply used for digital

• Low Cost

logic.

• Ultra-Low Input Current: 20 fA

Battery life is maximized because each amplifier

• High Voltage Gain @ V

=2.7V,

dissipates only micro-watts of power.

=100 kΩ: 120 dB

• Specified for 100 kΩ and 5 kΩ Loads

The LMC6574/2 does not sacrifice functionality for

low voltage operation. The LMC6574/2 generates

• Available in VSSOP Package

120 dB of open-loop gain just like a conventional

amplifier, but the LMC6574/2 can do this from a 2.7V

APPLICATIONS

supply.

• Transducer Amplifier

These amplifiers are designed with features that

• Portable or Remote Equipment

optimize low voltage operation. The output voltage

• Battery-Operated Instruments swings rail-to-rail to maximize signal-to-noise ratio

and dynamic signal range. The common-mode input

• Data Acquisition Systems

voltage range extends from 800 mV below the

• Medical Instrumentation

positive supply to 100 mV below ground.

• Improved Replacement for TLV2322 and

This device is built with Texas Instruments' advanced

TLV2324

Double-Poly Silicon-Gate CMOS process.

LMC6572 is also available in VSSOP package which

is almost half the size of a SOIC-8 device.

Connection Diagram

Figure 1. 8-Pin PDIP/SOIC/VSSOP Package

See Package Number P, D, or DGK

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (22 pages)

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LMC6572, LMC6574 www.ti.com SNOS707D – DECEMBER 1996 – REVISED MARCH 2013 LMC6572/LMC6574 Dual and Quad Low Voltage (2.7V and 3V) Operational Amplifier Check for Samples: LMC6572, LMC6574 FEATURES DESCRIPTION • • • Low voltage operation and low power dissipation make the LMC6574/2 ideal for battery-powered systems. 1 2 • • • • • • (Typical Unless Otherwise Noted) Guaranteed 2.
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LMC6572, LMC6574 SNOS707D – DECEMBER 1996 – REVISED MARCH 2013 www.ti.com Figure 2. 14-Pin PDIP/SOIC Package See Package Number NFF or D These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) ESD Tolerance (3) 2000V Differential Input Voltage ±Supply Voltage (V+) +0.3V, (V−) −0.
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LMC6572, LMC6574 www.ti.com SNOS707D – DECEMBER 1996 – REVISED MARCH 2013 2.7V DC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25°C. V+ = 2.7V, V− = 0V, VCM = VO = V+/2 and RL > 1MΩ. Boldface limits apply at the temperature extremes. Symbol VOS Parameter Input Offset Voltage Conditions V+ = 2.7V and 3V Typ (1) 0.5 TCVOS Input Offset Voltage Average Drift 1.5 IB Input Current 0.
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LMC6572, LMC6574 SNOS707D – DECEMBER 1996 – REVISED MARCH 2013 www.ti.com 2.7V DC Electrical Characteristics (continued) Unless otherwise specified, all limits guaranteed for TJ = 25°C. V+ = 2.7V, V− = 0V, VCM = VO = V+/2 and RL > 1MΩ. Boldface limits apply at the temperature extremes. Symbol ISC Parameter Output Short Circuit Current IS Supply Current Conditions Sourcing, VO = 0V Typ (1) LMC6574AI LMC6572AI Limit (2) LMC6574BI LMC6572BI Limit (2) 6.0 4.0 3.0 mA 3.0 2.0 Min 2.
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LMC6572, LMC6574 www.ti.com SNOS707D – DECEMBER 1996 – REVISED MARCH 2013 Typical Performance Characteristics VS = +3V, TA = 25°C, Unless otherwise specified Supply Current vs Supply Voltage (Dual Package) Input Current vs Temperature Figure 3. Figure 4. Sourcing Current vs Output Voltage Sinking Current vs Output Voltage Figure 5. Figure 6. Output Voltage Swing vs Supply Voltage Input Voltage Noise vs Frequency Figure 7. Figure 8.
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LMC6572, LMC6574 SNOS707D – DECEMBER 1996 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VS = +3V, TA = 25°C, Unless otherwise specified 6 Crosstalk Rejection vs Frequency Positive PSRR vs Frequency Figure 9. Figure 10. Negative PSRR vs Frequency CMRR vs Frequency Figure 11. Figure 12. Input Voltage vs Output Voltage (VS = ±1.5) Open Loop Frequency Response Figure 13. Figure 14.
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LMC6572, LMC6574 www.ti.com SNOS707D – DECEMBER 1996 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VS = +3V, TA = 25°C, Unless otherwise specified Open Loop Frequency Response vs Temperature Maximum Output Swing vs Frequency Figure 15. Figure 16. ZOUT vs Frequency Slew Rate vs Supply Voltage Figure 17. Figure 18. Non-Inverting Large Signal Pulse Response Non-Inverting Small Signal Pulse Response Figure 19. Figure 20.
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LMC6572, LMC6574 SNOS707D – DECEMBER 1996 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VS = +3V, TA = 25°C, Unless otherwise specified 8 Inverting Large Signal Pulse Response Inverting Small Signal Pulse Response Figure 21. Figure 22. Stability vs Capacitive Load Stability vs Capacitive Load Figure 23. Figure 24. Stability vs Capacitive Load Stability vs Capacitive Load Figure 25. Figure 26.
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LMC6572, LMC6574 www.ti.com SNOS707D – DECEMBER 1996 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VS = +3V, TA = 25°C, Unless otherwise specified Bandwidth vs Capacitive Load Capacitive Load vs Phase Margin Figure 27. Figure 28. Capacitive Load vs Gain Margin Figure 29.
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LMC6572, LMC6574 SNOS707D – DECEMBER 1996 – REVISED MARCH 2013 www.ti.com APPLICATIONS HINTS LOW VOLTAGE AMPLIFIER TOPOLOGY The LMC6574/2 incorporates a novel op-amp design topology that enables it to maintain rail-to-rail output swing even when driving a large load. Instead of relying on a push-pull unity gain output buffer stage, the output stage is taken directly from the internal integrator, which provides both low output impedance and large gain.
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LMC6572, LMC6574 www.ti.com SNOS707D – DECEMBER 1996 – REVISED MARCH 2013 Figure 31. LMC6574/2 Noninverting Gain of 10 Amplifier, Compensated to Handle Capacitive Loads In the circuit of Figure 31, R1 and C1 serve to counteract the loss of phase margin by feeding the high frequency component of the output signal back to the amplifier's inverting input, thereby preserving phase margin in the overall feedback loop.
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LMC6572, LMC6574 SNOS707D – DECEMBER 1996 – REVISED MARCH 2013 www.ti.com Figure 33. Inverting Amplifier Figure 34. Non-Inverting Amplifier Follower Figure 35.
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LMC6572, LMC6574 www.ti.com SNOS707D – DECEMBER 1996 – REVISED MARCH 2013 SPICE MACROMODEL A • • • • • spice macromodel is available for the LMC6574/2. This model includes accurate simulation of: input common-mode voltage range frequency and transient response GBW dependence on loading conditions quiescent and dynamic supply current output swing dependence on loading conditions and many more characteristics as listed on the macromodel disk.
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LMC6572, LMC6574 SNOS707D – DECEMBER 1996 – REVISED MARCH 2013 www.ti.com Figure 40. Adder/Subtractor Circuit Figure 41.
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LMC6572, LMC6574 www.ti.com SNOS707D – DECEMBER 1996 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision C (March 2013) to Revision D • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LMC6572AIMX/NOPB SOIC D LMC6572BIMX/NOPB SOIC LMC6574AIMX SOIC LMC6574AIMX/NOPB LMC6574BIMX/NOPB SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 5.4 2.0 8.0 12.0 Q1 8 2500 330.0 12.4 6.5 D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 D 14 2500 330.0 16.4 6.5 9.35 2.3 8.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMC6572AIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMC6572BIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMC6574AIMX SOIC D 14 2500 367.0 367.0 35.0 LMC6574AIMX/NOPB SOIC D 14 2500 367.0 367.0 35.0 LMC6574BIMX/NOPB SOIC D 14 2500 367.0 367.0 35.
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