Datasheet

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LMC8101

www.ti.com

SNOS496F –AUGUST 2000–REVISED MARCH 2013

LMC8101 Rail-to-Rail Input and Output, 2.7V Op Amp in

DSBGA Package With Shutdown

Check for Samples: LMC8101

FEATURES

DESCRIPTION

The LMC8101 is a Rail-to-Rail Input and Output high

• V

= 2.7V, T

= 25°C, R

to V

/2, Typical Values

performance CMOS operational amplifier. The

Unless Specified.

LMC8101 is ideal for low voltage (2.7V to 10V)

• Rail-to-Rail Inputs

applications requiring Rail-to-Rail inputs and output.

• Rail-to-Rail Output Swing Within 35mV of

The LMC8101 is supplied in the die sized DSBGA as

well as the 8 pin VSSOP packages. The DSBGA

Supplies (R

=2kΩ)

package requires 75% less board space as compared

• Packages Offered:

to the SOT-23 package. The LMC8101 is an upgrade

– DSBGA package 1.39mm x 1.41mm

to the industry standard LMC7101.

– VSSOP package 3.0mm x 4.9mm

The LMC8101 incorporates a simple user controlled

methodology for shutdown. This allows ease of use

• Low Supply Current <1mA (max)

while reducing the total supply current to 1nA typical.

This extends battery life where power saving is

• Shutdown Current 1µA (Max)

mandated. The shutdown input threshold can be set

• Versatile Shutdown Feature 10µs Turn-On

relative to either V

or V

−

using the SL pin (see

• Output Short Circuit Current 10mA

Application Notes section for details).

• Offset Voltage ±5 mV (max)

Other enhancements include improved offset voltage

• Gain-Bandwidth 1MHz

limit, three times the output current drive and lower

1/f noise when compared to the industry standard

• Supply Voltage Range 2.7V-10V

LMC7101 Op Amp. This makes the LMC8101 ideal

• THD 0.18%

for use in many battery powered, wireless

• Voltage Noise 36nv/√Hz

communication and Industrial applications.

APPLICATIONS

• Portable Communication (Voice, Data)

• Cellular Phone Power Amp Control Loop

• Buffer AMP

• Active Filters

• Battery Sense

• VCO Loop

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (25 pages)

PAGE 1
LMC8101 www.ti.com SNOS496F – AUGUST 2000 – REVISED MARCH 2013 LMC8101 Rail-to-Rail Input and Output, 2.7V Op Amp in DSBGA Package With Shutdown Check for Samples: LMC8101 FEATURES DESCRIPTION 1 • 2 • • • • • • • • • • • • + VS = 2.7V, TA = 25°C, RL to V /2, Typical Values Unless Specified. Rail-to-Rail Inputs Rail-to-Rail Output Swing Within 35mV of Supplies (RL =2kΩ) Packages Offered: – DSBGA package 1.39mm x 1.41mm – VSSOP package 3.0mm x 4.
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LMC8101 SNOS496F – AUGUST 2000 – REVISED MARCH 2013 www.ti.com Connection Diagrams A2 + V A3 SL A1 + V B1 OUTPUT B3 INVERTING INPUT C1 SD - C3 NONINVERTING INPUT V C2 Figure 1. 8-Pin VSSOP Top View Figure 2. DSBGA Top View These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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LMC8101 www.ti.com SNOS496F – AUGUST 2000 – REVISED MARCH 2013 Operating Ratings Supply Voltage (V+ - V−) 2.7V to 10V Junction Temperature Range (2) Package Thermal Resistance (θJA) (2) (1) −40°C to +85°C DSBGA 220°C/W VSSOP package 8 pin Surface Mount 230°C/W Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not specified.
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LMC8101 SNOS496F – AUGUST 2000 – REVISED MARCH 2013 www.ti.com 2.7V Electrical Characteristics (continued) Unless otherwise specified, all limits specified for TJ = 25°C, V+ = 2.7V, V− = 0V, VCM = VO = V+/2 and RL > 1 MΩ to V+/2. Boldface limits apply at the temperature extremes. Symbol Typ (1) Limit (2) Units V+/2 (4) Sourcing to VID = 100mV 20 14 6 mA min Sinking to V+/2 VID = −100mV (4) 10 5 4 mA min 1.0 1.
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LMC8101 www.ti.com SNOS496F – AUGUST 2000 – REVISED MARCH 2013 ±5V Electrical Characteristics (continued) Unless otherwise specified, all limits specified for TJ = 25°C, V+ =5V, V− = −5V, VCM = VO = 0V, and RL > 1 MΩ to gnd. Boldface limits apply at the temperature extremes. Symbol Typ (1) Limit (2) Sourcing RL = 600Ω VO = 0V to 4V 34.5 17.8 10 Sinking RL = 600Ω VO = 0V to −4V 34.5 17.8 3.16 Sourcing RL = 2kΩ VO = 0V to 4.6V 138 31.6 17.8 Sinking RL = 2kΩ VO = 0V to −4.
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LMC8101 SNOS496F – AUGUST 2000 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics VS = 2.7V, Single Supply, VCM = V+/2, TA = 25°C unless specified 6 Gain/Phase vs. Frequency (RL = 2k, VS = ± 1.35V) Gain/Phase vs. Frequency (RL = 2k, VS = ± 5V) Figure 3. Figure 4. Gain/Phase vs. Frequency (RL = Open) Gain vs. Phase for various CL VS = ±1.35V Figure 5. Figure 6. Unity Gain Frequency vs. Supply Voltage Phase Margin vs. Supply Voltage Figure 7. Figure 8.
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LMC8101 www.ti.com SNOS496F – AUGUST 2000 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VS = 2.7V, Single Supply, VCM = V+/2, TA = 25°C unless specified Unity Gain Frequency and Phase Margin vs. Load Unity Gain Frequency and Phase Margin vs. Load Figure 9. Figure 10. PSRR vs. Frequency PSRR vs. Frequency Figure 11. Figure 12. CMRR vs. Frequency Input Bias Current vs. Common Mode Voltage @ 85°C Figure 13. Figure 14.
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LMC8101 SNOS496F – AUGUST 2000 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VS = 2.7V, Single Supply, VCM = V+/2, TA = 25°C unless specified 8 Input Current vs. Temperature VS = 10V VIN vs. VOUT Figure 15. Figure 16. VIN vs. VOUT VIN vs. VOUT Figure 17. Figure 18. VIN vs. VOUT Supply Current vs. Supply Voltage Figure 19. Figure 20.
PAGE 9
LMC8101 www.ti.com SNOS496F – AUGUST 2000 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VS = 2.7V, Single Supply, VCM = V+/2, TA = 25°C unless specified Delta VOS vs. VCM (Ref VCM = 1.35V) Delta VOS vs. VCM (Ref VCM = 5V) Figure 21. Figure 22. Offset Voltage vs. VSUPPLY Output Positive Swing vs. Supply Voltage RL = 600Ω to V+/2 Figure 23. Figure 24. Output Positive Swing vs. Supply Voltage RL = 2k to V+/2 Output Negative Swing vs.
PAGE 10
LMC8101 SNOS496F – AUGUST 2000 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VS = 2.7V, Single Supply, VCM = V+/2, TA = 25°C unless specified 10 Output Negative Swing vs. Supply Voltage, RL = 2k to V+/2 Short Circuit Sinking Current vs. Supply Voltage Figure 27. Figure 28. Short Circuit Sourcing Current vs. Supply Voltage Undistorted Output Voltage Swing vs. Output Load Resistance Figure 29. Figure 30. Step Response 1% settling time and % overshoot vs.
PAGE 11
LMC8101 www.ti.com SNOS496F – AUGUST 2000 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VS = 2.7V, Single Supply, VCM = V+/2, TA = 25°C unless specified Small Signal Step Response Large Signal Step Response Figure 33. Figure 34. Small Signal Step Response Small Signal Step Response Figure 35. Figure 36. Large Signal Step Response Large Signal Step Response Figure 37. Figure 38.
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LMC8101 SNOS496F – AUGUST 2000 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VS = 2.7V, Single Supply, VCM = V+/2, TA = 25°C unless specified 12 Small Signal Step Response Slew Rate vs. Supply Voltage Figure 39. Figure 40. Slew Rate vs. Capacitive Load Slew Rate vs. Capacitive Load Figure 41. Figure 42. Slew Rate vs. Capacitive Load Slew Rate vs. Capacitive Load Figure 43. Figure 44.
PAGE 13
LMC8101 www.ti.com SNOS496F – AUGUST 2000 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VS = 2.7V, Single Supply, VCM = V+/2, TA = 25°C unless specified Voltage Noise vs. Frequency Voltage Noise vs. VCM @ Various Frequencies Figure 45. Figure 46. THD+N vs. Amplitude THD+N vs. Frequency Figure 47. Figure 48. Sourcing Current vs. Output Voltage (VS = 2.7V) Sinking Current vs. Output Voltage (VS = 2.7V) Figure 49. Figure 50.
PAGE 14
LMC8101 SNOS496F – AUGUST 2000 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VS = 2.7V, Single Supply, VCM = V+/2, TA = 25°C unless specified 14 Sourcing Current vs. Output Voltage (VS = 10V) Sinking Current vs. Output Voltage (VS = 10V) Figure 51. Figure 52. Cap Load vs. IOUT Cap Load vs. Isolation Resistance Figure 53. Figure 54.
PAGE 15
LMC8101 www.ti.com SNOS496F – AUGUST 2000 – REVISED MARCH 2013 APPLICATION NOTES SHUTDOWN FEATURES The LMC8101 is capable of being turned off in order to conserve power. Once in shutdown, the device supply current is drastically reduced (1µA maximum) and the output will be "Tri-stated". The shutdown feature of the LMC8101 is designed for flexibility. The threshold level of the SD input can be referenced to either V-or V+ by setting the level on the SL input.
PAGE 16
LMC8101 SNOS496F – AUGUST 2000 – REVISED MARCH 2013 www.ti.com CONVERSION BOARDS In order to ease the evaluation of tiny packages such as the DSBGA, there is a conversion board (LMC8101CONV) available to board designers. This board converts a DSBGA device into an 8 pin DIP package (see Figure 56) for easier handling and evaluation. This board can be ordered from Texas Instruments by contacting http://www.ti.com. Figure 56.
PAGE 17
LMC8101 www.ti.com SNOS496F – AUGUST 2000 – REVISED MARCH 2013 This resistor will isolate the feedback path (where excessive phase shift due to output capacitance can cause instability) from the capacitive load. With a 10V supply, a 100Ω isolation resistor allows unlimited capacitive load without oscillation compared to only 300pF without this resistor (AV = +1). • Higher supply voltage: Operating the LMC8101 at higher supply voltages allows higher cap load tolerance.
PAGE 18
LMC8101 SNOS496F – AUGUST 2000 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision E (March 2013) to Revision F • 18 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMC8101MM VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMC8101MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMC8101MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMC8101MM VSSOP DGK 8 1000 210.0 185.0 35.0 LMC8101MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LMC8101MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LMC8101TP/NOPB DSBGA YPB 8 250 210.0 185.0 35.0 LMC8101TPX/NOPB DSBGA YPB 8 3000 210.0 185.0 35.
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MECHANICAL DATA YPB0008 D 0.5±0.045 E TPA08XXX (Rev A) D: Max = 1.464 mm, Min =1.403 mm E: Max = 1.464 mm, Min =1.403 mm 4215100/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. This drawing is subject to change without notice. www.ti.
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