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LMH0030

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SNLS219G –JANUARY 2006–REVISED APRIL 2013

EDH REGISTERS 0, 1 AND 2 (Addresses 01h through 03h)

Updated EDH packets may be inserted into the serial output data by setting the EDH Force bit in the control

registers. The EDH Force control bit causes the insertion of new EDH checkwords and flags into the serial

output regardless of the previous condition of EDH checkwords and flags in the input parallel data. This function

may be used in situations where video content has been editted thus making the previous EDH information

invalid. In the case of SMPTE 292M data, the CRC check characters are recalculated and inserted automatically

regardless of the presence of CRC characters in the parallel data. After the LMH0030 is reset, the initial state of

the CRC check characters is 00h.

The EDH Enable bit enables operation of the EDH generator function.

The EDH ERROR (SD) bit when set indicates that EDH error conditions are being reported in EDH ancillary data

packets present in the parallel input data. Details of the specific error conditions contained in the EDH packets

are reported via the full field, active picture and ancillary flag error bits and the specific flag bits in these registers.

The EDH flags F/F FLAGS[4:0] (full field), A/P FLAGS[4:0] (active picture) and ANC FLAGS[4:0] (ancillary

data) are defined in SMPTE RP 165. The EDH flags are stored in the control registers. The flags are updated

automatically when the EDH function is enabled and data is being received.

The status of EDH flag errors in incoming SD parallel data are reported in the ffFlagError, apFlagError and

ancFlagError bits. The ffFlagError, apFlagError and ancFlagError bits are the logical-OR of the corresponding

EDH and EDA flags of the EDH checkwords.

ANC REGISTER 0 (Address 04h)

The V FIFO Depth[2:0] bits control the depth of the video FIFO which follows the input data latches. The depth

can be set from 0 to 4 stages deep by writing the corresponding binary code into these bits. For example: to set

the Video FIFO depth at two registers, load 11010XXXXXb into the ANC 0 control register (where X represents

the other functional bits of this register). To retain other data previously stored in a register, read the register’s

contents and logically-OR this with the new data. Then write the composite data back into the register.

Flags for FIFO EMPTY, FIFO FULL and FIFO OVERRUN are available in the configuration and control register

set. These flags can also be assigned as inputs and outputs on the multi-function I/O port. The FIFO OVERRUN

flag indicates that an attempt to write data into a full FIFO has occurred.

The ANC Checksum Force bit, under certain conditions, enables the overwriting of ancillary data checksums

received in the parallel ancillary data. Calculation and insertion of new ancillary data checksums is controlled by

the ANC Checksum Force bit. If a checksum error is detected (calculated and received checksums do not

match) and the ANC Checksum Force bit is set, a new checksum will be inserted in the ancillary data replacing

the previous one. If a checksum error is detected and the ANC Checksum Force bit is not set, the checksum

mismatch is reported via the ANC Checksum Error bit.

Ancillary data checksums may be received in the incoming parallel ancillary data. Alternatively they may be

calculated and inserted automatically by the LMH0030. The CHKSUM ATTACH IN bit in the control registers

when set to a logic-1 indicates that the checksum is to be supplied in the incoming data. When the CHKSUM

ATTACH IN bit is set, checksums for incoming data are calculated and checked against received checksums.

Calculation and insertion of new ancillary data checksum is controlled by the ANC Checksum Force bit in the

configuration and control registers. If a checksum error is detected (calculated and received checksums do not

match) and the ANC Checksum Force bit is set, a new checksum will be inserted in the ancillary data replacing

the previous one. If a checksum error is detected and the ANC Checksum Force bit is not set, the checksum

mismatch is reported via the ANC CHECKSUM ERROR bit in the control registers.

The ANC Checksum Error bit indicates that the received ancillary data checksum did not agree with the

LMH0030's internally generated checksum. This bit is available as an output on the multifunction I/O port.

ANC REGISTERS 1 THROUGH 4 (Address 05h through 08h)

Admission of ancillary data packets into the FIFO can be controlled by the ANC MASK[15:0] and ANC ID[15:0]

bits in the control registers. The ANC ID[7:0] register can be set to a valid 8-bit Data Identification (DID) code

used for component ancillary data packet identification as specified in SMPTE 291M. Similarly, theANC ID[15:8]

ANC MASK[7:0] is an 8-bit word that can be used to selectively control loading of packets with specific DIDs (or

DID ranges) into the FIFO. Similarly, the ANC MASK[15:8] is an 8-bit word that can be used to selectively

control loading of packets with specific SDID or DBNs (or SDID or DBN ranges).

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