Datasheet

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LMH0031

www.ti.com

SNLS218A –JANUARY 2006–REVISED APRIL 2013

LMH0031 SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video

and Ancillary Data FIFOs

Check for Samples: LMH0031

FEATURES

APPLICATIONS

• SDTV/HDTV Serial Digital Video Standard

• SDTV/HDTV Serial-to-Parallel Digital Video

Compliant Interfaces for:

• Supports 270 Mbps, 360 Mbps, 540 Mbps, – Video Editing Equipment

1.483 Gbps and 1.485 Gbps Serial Video Data

– VTRs

Rates with Auto-Detection

– Standards Converters

• LSB De-Dithering Option

– Digital Video Routers and Switchers

• Uses Low-Cost 27MHz Crystal or Clock

– Digital Video Processing and Editing

Oscillator Reference

Equipment

• Fast VCO Lock Time: < 500 µs at 1.485 Gbps

– Video Test Pattern Generators and Digital

• Built-in Self-Test (BIST) and Video Test Pattern

Video Test Equipment

Generator (TPG)

– Video Signal Generators

(1)

Patent Applications Made or Pending

DESCRIPTION

• Automatic EDH/CRC Word and Flag

Processing

The LMH0031 SMPTE 292M / 259M Digital Video

Deserializer/Descrambler with Video and Ancillary

• Ancillary Data FIFO with Extensive Packet

Data FIFOs is a monolithic integrated circuit that

Handling Options

deserializes and decodes SMPTE 292M, 1.485Gbps

• Adjustable, 4-Deep Parallel Output Video Data

(or 1.483Gbps) serial component video data, to 20-bit

FIFO

parallel data with a synchronized parallel word-rate

clock. It also deserializes and decodes SMPTE 259M,

• Flexible Control and Configuration I/O Port

270Mbps, 360Mbps and SMPTE 344M (proposed)

• LVCMOS Compatible Control Inputs and Clock

540Mbps serial component video data, to 10-bit

and Data Outputs

parallel data. Functions performed by the LMH0031

• LVDS and ECL-Compatible, Differential, Serial

include: clock/data recovery from the serial data,

Inputs

serial-to-parallel data conversion, SMPTE standard

data decoding, NRZI-to-NRZ conversion, parallel data

• 3.3V I/O Power Supply and 2.5V Logic Power

clock generation, word framing, CRC and EDH data

Supply Operation

checking and handling, Ancillary Data extraction and

• Low Power: Typically 850mW

automatic video format determination. The parallel

• 64-Pin TQFP Package

video output features a variable-depth FIFO which

can be adjusted to delay the output data up to 4

• Commercial Temperature Range 0°C to +70°C

parallel data clock periods. Ancillary Data may be

selectively extracted from the parallel data through

the use of masking and control bits in the

configuration and control registers and stored in the

on-chip FIFO. Reverse LSB dithering is also

implemented.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (39 pages)

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LMH0031 www.ti.com SNLS218A – JANUARY 2006 – REVISED APRIL 2013 LMH0031 SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancillary Data FIFOs Check for Samples: LMH0031 FEATURES APPLICATIONS • • 1 2 • • • • • (1) • • • • • • • • • • SDTV/HDTV Serial Digital Video Standard Compliant Supports 270 Mbps, 360 Mbps, 540 Mbps, 1.483 Gbps and 1.
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LMH0031 SNLS218A – JANUARY 2006 – REVISED APRIL 2013 www.ti.com DESCRIPTION (CONTINUED) The unique multi-functional I/O port of the LMH0031 provides external access to functions and data stored in the configuration and control registers. This feature allows the designer greater flexibility in tailoring the LMH0031 to the desired application. The LMH0031 is auto-configured to a default operating condition at power-on or after a reset command.
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LMH0031 www.ti.
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LMH0031 SNLS218A – JANUARY 2006 – REVISED APRIL 2013 www.ti.
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LMH0031 www.ti.com SNLS218A – JANUARY 2006 – REVISED APRIL 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) CMOS I/O Supply Voltage (VDDIO–VSSIO): 4.0V SDI Supply Voltage (VDDSI–VSSSI): 4.0V Digital Logic Supply Voltage (VDDD–VSSD): 3.0V PLL Supply Voltage (VDDPLL–VSSPLL): 3.
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LMH0031 SNLS218A – JANUARY 2006 – REVISED APRIL 2013 www.ti.com Required Input Conditions (1) (2) Symbol Parameter VIN Input Voltage Range tr, tf Rise Time, Fall Time Conditions 10%–90% Reference Min 1.
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LMH0031 www.ti.com SNLS218A – JANUARY 2006 – REVISED APRIL 2013 DC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (1) (2). Symbol Parameter Conditions VIH Input Voltage High Level VIL Input Voltage Low Level IIH Input Current High Level VIH = VDDIO (3) IIL Input Current Low Level VIL = VSSIO VOH Output Voltage High Level IOH = −2 mA Reference All LVCMOS Inputs Min Typ 2.0 VDDIO VSSIO 0.8 +85 +150 −1 −20 2.4 2.
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LMH0031 SNLS218A – JANUARY 2006 – REVISED APRIL 2013 www.ti.com AC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (1). Symbol Parameter Conditions Reference Min Typ Max Units Serial Video Data Inputs BRSDI Serial Input Data Rate SMPTE 259M, Level C 270 SMPTE 259M, Level D 360 SMPTE 344M 540 SMPTE 292M 1,483 SDI, SDI SMPTE 292M tr, tf Rise Time, Fall Time MBPS 1,485 20%–80%, SMPTE 259M Data Rates 0.4 1.
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LMH0031 www.ti.com SNLS218A – JANUARY 2006 – REVISED APRIL 2013 Test Loads VDDIO IOL Hi-Z test eqpt. t 5k: (attenuation 0dB) S1 CMOS outputs IOH CL S2 CL including probe and jig capacitance, 3pF max.
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LMH0031 SNLS218A – JANUARY 2006 – REVISED APRIL 2013 www.ti.com Test Circuit SDI 1.0 PF +2.5 Vdc (x4) 82.5: 1 nF (x4) 825: (x2) 0.1 PF 4.7 PF 16V 0.1 PF 4.7 PF 16V (x2) +3.3 Vdc 53 61 4.75k 27 MHz CLK.
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LMH0031 www.ti.com SNLS218A – JANUARY 2006 – REVISED APRIL 2013 Timing Diagram 90% 90% VCLK (ACLK) 50% tr, tf 10% 10% tH tS 90% AD[9:0] INPUT DATA tr, tf 10% tPD DV[19:0] OUTPUT DATA tPD AD[9:0] OUTPUT DATA Device Operation INTRODUCTION The LMH0031 SMPTE 292M/259M Digital Video Deserializer/Decoder is used in digital video signal origination and destination equipment: cameras, video tape recorders, telecines, editors, standards converters, video test and other equipment.
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LMH0031 SNLS218A – JANUARY 2006 – REVISED APRIL 2013 www.ti.com LMH0031 1 PF SDI 82.5: 825: 1 PF SDI 82.5: 825: RBB RREF 1 nF 8.66 k: 4.75 k: Figure 2. Optional Input Biasing Scheme The SMPTE descrambler receives NRZI serial data, converts it to NRZ, then decodes it to either 10-bit standard definition or 20-bit high definition parallel video data using the reverse polynomial X9 + X4 + 1 as specified in the respective standard: SMPTE 259M, SMPTE 344M (proposed) or SMPTE 292M.
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LMH0031 www.ti.com SNLS218A – JANUARY 2006 – REVISED APRIL 2013 Once the PLL attains lock, the video format detector processes the received data to determine the raster characteristics (video data format) and configure the LMH0031 to handle it. This assures that the parallel output data will be properly formatted, that the correct data rate is selected and that Ancillary Data and CRC/EDH data are correctly detected and checked.
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LMH0031 SNLS218A – JANUARY 2006 – REVISED APRIL 2013 www.ti.com immediately following the rising edge of ACLK or when the address signal is removed. For optimum system timing, the signals driving the address to the port should be removed immediately after the address is clocked into the port and before or simultaneously with the falling edge of ACLK at the end of that address cycle.
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LMH0031 www.ti.com SNLS218A – JANUARY 2006 – REVISED APRIL 2013 Figure 4. Control Data Write Timing Ancillary Data Functions The LMH0031 can recover Ancillary Data from the serial data stream. This Ancillary Data and related control characters are defined in the relevant SMPTE standards and may reside in the horizontal and vertical blanking intervals. The data can consist of different types of message packets including audio data. The serial Ancillary Data space must be formatted according to SMPTE 291M.
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LMH0031 SNLS218A – JANUARY 2006 – REVISED APRIL 2013 www.ti.com ACLK RD/WR ANC/CTRL READ AD[9:0] DATA DATA DATA DATA DATA DATA Figure 5. Ancillary Data Read Timing MULTI-FUNCTION I/O PORT The multi-function I/O port can be configured to provide immediate access to many control and indicator functions that are stored within the LMH0031’s configuration and control registers.
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LMH0031 www.ti.com SNLS218A – JANUARY 2006 – REVISED APRIL 2013 EDH/CRC SYSTEM The LMH0031 has EDH and CRC character generation and checking circuitry. The EDH system functions as described in SMPTE Recommended Practice RP-165. The CRC system functions as specified in SMPTE 292M. The EDH/CRC polynomial generators/checkers accept parallel data from the de-serializing system and generate the EDH and CRC check words for comparison with those received in the data.
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LMH0031 SNLS218A – JANUARY 2006 – REVISED APRIL 2013 www.ti.com The LMH0031 indicates that the PLL is locked to the incoming data rate and that the CDR has acquired a phase of the serial data by setting the Lock Detect bit in the Video Info 0 control register. Indication of the standard being processed is retained in the FORMAT[4:0] bits in the FORMAT 1 control data register. Format data from this register can be programmed for output on the multi-function I/O port.
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LMH0031 www.ti.com SNLS218A – JANUARY 2006 – REVISED APRIL 2013 4. Toggle ACLK. 5. Present 343h to AD[9:0] as the register data (525 line, 30 frame, 27MHz, NTSC 4x3, colour bars (SMPTE 125M)). 6. Toggle ACLK. 7. The PASS/FAIL indicator, TEST 0 register, Bit 7, should be read for the result of the test. Alternatively, this bit may be mapped to a convenient bit of the Multi-function I/O bus. The test pattern data and clock is available at the DV[19:0] and VCLK outputs.
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LMH0031 SNLS218A – JANUARY 2006 – REVISED APRIL 2013 www.ti.com Table 1.
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LMH0031 www.ti.com SNLS218A – JANUARY 2006 – REVISED APRIL 2013 Table 2.
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LMH0031 SNLS218A – JANUARY 2006 – REVISED APRIL 2013 www.ti.com Table 3.
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LMH0031 www.ti.com SNLS218A – JANUARY 2006 – REVISED APRIL 2013 EDH 2 (register 03h) The EDH Ancillary Data flags ANC UES, ANC IDA, ANC IDH, ANC EDA andANC EDH are defined in SMPTE RP 165. The flags are updated automatically when the EDH function is enabled and data is being received. The status of EDH flag errors in incoming SD serial data are reported in the ffFlagError, apFlagError and ancFlagError bits. Each of these bits is the logical-OR of the corresponding EDH and EDA flags.
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LMH0031 SNLS218A – JANUARY 2006 – REVISED APRIL 2013 www.ti.com ANC 5 (Address 17h) The FIFO EXTRACT ENABLE bit in the control registers enables the device to extract or copy Ancillary Data from the video data stream and place it in the ANC FIFO. From there data may be output via the parallel ancillary port. Data extraction is enabled when this bit is set to a logic-1. This bit can be used to delay automatic extraction and therefore the output of parallel Ancillary Data.
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LMH0031 www.ti.com SNLS218A – JANUARY 2006 – REVISED APRIL 2013 Table 4. Video Raster Format Parameters Format Code [4,3,2,1,0] (1) Format Spec. (1) Frame Rate Lines Active Lines Samples Active Samples 00001 SDTV, 54 RP 174 60I 525 507/487* 3432 2880 00010 SDTV, 36 SMPTE 267 60I 525 507/487* 2288 1920 00011 SDTV, 27 SMPTE 125 60I 525 507/487* 1716 1440 01001 SDTV, 54 ITU-R BT 601.5 50I 625 577 3456 2880 01010 SDTV, 36 ITU-R BT 601.
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LMH0031 SNLS218A – JANUARY 2006 – REVISED APRIL 2013 www.ti.com TEST 0 REGISTER (Address 0Dh) The Test Pattern Select bits determine which test pattern is output when the Test Pattern Generator (TPG) mode or the Built-in Self-Test (BIST) mode is enabled. Table 5 gives the codes corresponding to the various test patterns. All HD colour bar test patterns are inherently BIST data. BIST test patterns for SD are: NTSC, 27MHz, 4x3 Colour Bars and PAL, 27MHz, 4x3 PLL Pathological.
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LMH0031 www.ti.com SNLS218A – JANUARY 2006 – REVISED APRIL 2013 Table 5. Test Pattern Selection Codes(1) (continued) Test Pattern Select Word Bits > Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Colour Bars 1 1 1 0 1 1 750 Line, 74.25 MHz, 60 Frame Progressive Component (SMPTE 296M) Ref. Black 1 1 1 1 0 0 PLL Path. 1 1 1 1 0 1 EQ Path. 1 1 1 1 1 0 Colour Bars 1 1 1 1 1 1 525 Line, 30 Frame, 27 MHz, NTSC 4x3 (SMPTE 125M) Ref. Black 0 0 0 0 0 0 PLL Path.
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LMH0031 SNLS218A – JANUARY 2006 – REVISED APRIL 2013 www.ti.com The Lock Detect is a logic-1 when the loop is locked and the CDR has acquired a phase of the incoming serial data. This bit may be programmed as an output on the multi-function I/O bus. This bit is mapped to I/O port bit 4 in the default condition. The VPG Filter Enable bit when set enables operation of the Video Pattern Generator filter.
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LMH0031 www.ti.com SNLS218A – JANUARY 2006 – REVISED APRIL 2013 Example: Program, via the AD port, I/O port bit 0 as output for the CRC Luma Error bit in the control registers. 1. Set ANC/CTRL to a logic-low. 2. Set RD/WR to a logic-low. 3. Present 00Fh to AD[9:0] as the I/O PIN 0 CONFIG register address. 4. Toggle ACLK. 5. Present 310h to AD[9:0] as the register data, the bit address of the CRC Luma Error bit in the control registers. 6. Toggle ACLK. Table 6.
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LMH0031 SNLS218A – JANUARY 2006 – REVISED APRIL 2013 www.ti.com Table 6.
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LMH0031 www.ti.com SNLS218A – JANUARY 2006 – REVISED APRIL 2013 PIN DESCRIPTIONS (continued) Pin Name Description 37 DV6 Parallel Video Output (HD=Chroma, SD=Luma & Chroma) 38 DV5 Parallel Video Output (HD=Chroma, SD=Luma & Chroma) 39 VSSD Negative Power Supply Input (2.
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LMH0031 SNLS218A – JANUARY 2006 – REVISED APRIL 2013 www.ti.com Application Information A typical application circuit for the LMH0031 is shown in the Application Circuit diagram. This circuit demonstrates the capabilities of the LMH0031 and allows its evaluation in a native configuration. An assembled demonstration board is available, part number SD131EVK. The board may be ordered through any of TI's sales offices.
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LMH0031 www.ti.com SNLS218A – JANUARY 2006 – REVISED APRIL 2013 PROCESSING NON-SUPPORTED RASTER FORMATS The number and type of HD raster formats has proliferated since the LMH0031 was designed. Though not specifically capable of fully or automatically processing these new formats, the LMH0031 may still be capable of deserializing them.
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LMH0031 SNLS218A – JANUARY 2006 – REVISED APRIL 2013 www.ti.com +3.3V LMC7101 NC7SZ126 VCTRL + - 74.25 MHz VCXO FOUT OE 22.1: 100 k: +3.3V 182 k: NC7SZ125 VCTRL 27.00 MHz VCXO FOUT OE 22.1: CLC031 IO3 - SD/HD CLC031 IO4 - Lock Detect NC7SZ08 RB B VCLK LMH0031 22.1 k: 100 pF 10 nF RREF 4.75 k: To other logic or serializer DV[19:0] CAUTION! Read text before using this circuit. Figure 8.
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LMH0031 www.ti.com SNLS218A – JANUARY 2006 – REVISED APRIL 2013 REVISION HISTORY Changes from Original (April 2013) to Revision A • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 24-Nov-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 48 0,08 M 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4040282 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.