Datasheet

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Control

SMPTE Cable Driver

LOCK

RESET

SCK

SDA

SMBus

TXOUT

PLL Clock

Generation

LVDS Receivers

TXCLK

TX0

TX1

TX2

TX3

TX4

Bypassable 8b10b Encode

Parallel to Serial 5:1

SMB_CS

DVB_ASI

GPIO[2:0]

LMH0040, LMH0050

LMH0070, LMH0340

www.ti.com

SNLS271I –APRIL 2007–REVISED APRIL 2013

3 Gbps, HD, SD, DVB-ASI SDI Serializer and Cable Driver With LVDS Interface

Check for Samples: LMH0040, LMH0050, LMH0070, LMH0340

FEATURES

DESCRIPTION

The LMH0340/0040/0070/0050 SDI Serializers are

• LVDS Interface to Host FPGA

part of TI’s family of FPGA-Attach SER/DES products

• No External VCO or Clock Ref Required

supporting 5-bit LVDS interfaces with FPGAs. An

• Integrated Variable Output Cable Driver

FPGA Host will format data with supplied IP such that

the output of the LMH0340 is compliant with the

• 3.3V SMBus Configuration Interface

requirements of DVB-ASI, SMPTE 259M-C, SMPTE

• Integrated TXCLK PLL Cleans Clock Noise

292M and SMPTE 424M standards. See Table 1 for

• Small 48-Pin WQFN Package

details on which Standards are supported per device.

• Industrial Temperature range: -40°C to 85°C

The interface between the SER (Serializer) and the

FPGA consists of a 5 bit wide LVDS data bus, an

APPLICATIONS

LVDS clock and an SMBus interface. The

LMH0340/0040/0070 SER devices include an

• SDI Unterfaces for:

integrated cable driver which is fully compliant with all

– Video Cameras

of the SMPTE specifications listed above. The

– DVRs

LMH0050 has a CML output driver that can drive a

differential transmission line or interface to a cable

– Video Switchers

driver.

– Video Editing Systems

The FPGA-Attach SER/DES family is supported by a

suite of IP which allows the design engineer to

KEY SPECIFICATIONS

quickly develop video applications using the

• Output Compliant With SMPTE 424M, SMPTE

SER/DES products. The SER is packaged in a

292M, SMPTE 259M-C and DVB-ASI (See

physically small 48-pin WQFN package.

Table 1)

• Typical Power Dissipation: 440 mW

General Block Diagram

• 30 ps Typical Output Jitter (HD, 3G)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (30 pages)

PAGE 1
LMH0040, LMH0050 LMH0070, LMH0340 www.ti.com SNLS271I – APRIL 2007 – REVISED APRIL 2013 3 Gbps, HD, SD, DVB-ASI SDI Serializer and Cable Driver With LVDS Interface Check for Samples: LMH0040, LMH0050, LMH0070, LMH0340 FEATURES DESCRIPTION • • • • • • • The LMH0340/0040/0070/0050 SDI Serializers are part of TI’s family of FPGA-Attach SER/DES products supporting 5-bit LVDS interfaces with FPGAs.
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LMH0040, LMH0050 LMH0070, LMH0340 SNLS271I – APRIL 2007 – REVISED APRIL 2013 www.ti.
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LMH0040, LMH0050 LMH0070, LMH0340 www.ti.com SNLS271I – APRIL 2007 – REVISED APRIL 2013 PIN DESCRIPTIONS Pin Name Type Description TX[4:0]+ TX[4:0]- Input, LVDS LVDS Data Input Pins Five channel wide DDR interface. Internal 100Ω termination. TXCLK+ TXCLK- Input, LVDS LVDS Clock Input Pins DDR Interface. Internal 100Ω termination.
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LMH0040, LMH0050 LMH0070, LMH0340 SNLS271I – APRIL 2007 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) −0.3V to +4.0V Supply Voltage (VDD3V3) −0.3V to +3.0V Supply Voltage (VDD2V5) LVCMOS input voltage −0.3V to (VDD3V3+0.3V) LVCMOS output voltage −0.3V to (VDD3V3+0.
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LMH0040, LMH0050 LMH0070, LMH0340 www.ti.com SNLS271I – APRIL 2007 – REVISED APRIL 2013 Electrical Characteristics Over supply and Operating Temperature ranges unless otherwise specified. Symbol Parameter Condition IDD2.5 2.5V supply current for LMH0340, LMH0040, or LMH0070 2.5V supply current for LMH0050 IDD3.3 3.3V supply current for LMH0340, LMH0040, or LMH0070 3.3V supply current for LMH0050 PD (1) Power Consumption (1) Min Typ Max Units 2.97 Gbps 93 102 mA 1.
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LMH0040, LMH0050 LMH0070, LMH0340 SNLS271I – APRIL 2007 – REVISED APRIL 2013 www.ti.com LVDS Switching Characteristics Over supply and Operating Temperature ranges unless otherwise specified. (1) Symbol Parameter Condition Min tCIP TxCLKIN Period See Figure 2 3.2 tCIT TxCLKIN Transition Time See Figure 3 0.5 tCIH TxCLKIN IN High Time See Figure 2 0.7T tCIL TxCLKIN IN Low Time See Figure 2 0.
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LMH0040, LMH0050 LMH0070, LMH0340 www.ti.com SNLS271I – APRIL 2007 – REVISED APRIL 2013 SMBus Switching Characteristics Over supply and Operating Temperature ranges unless otherwise specified. (1) Symbol Parameter fSMB Bus Operating Frequency 10 tBUF Bus free time between stop and start condition 4.7 μs tHD:STA Hold time after (repeated) start condition. After this period, the first clock is generated 4.0 μs tSU:STA Repeated Start condition setup time 4.
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LMH0040, LMH0050 LMH0070, LMH0340 SNLS271I – APRIL 2007 – REVISED APRIL 2013 www.ti.com SDI Output Characteristics — LMH0340 / LMH0040 / LMH0070 (continued) Over supply and Operating Temperature ranges unless otherwise specified. (1) Symbol Parameter Condition Δtt Mismatch between rise and fall time ≥1.485 Gbps tSD Propagation Delay Latency See Figure 5 tJ Peak to Peak Alignment Jitter ≥1.485 Gbps (3) 30 50 270 Mbps (3) 100 200 RL tOS (2) (3) (4) Min Typ (2) Max Units 30 ps 9.
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LMH0040, LMH0050 LMH0070, LMH0340 www.ti.com SNLS271I – APRIL 2007 – REVISED APRIL 2013 FUNCTIONAL DESCRIPTION DEVICE OPERATION The SER is used in digital video signal origination equipment. It is intended to be operated in conjunction with an FPGA host which preprocesses data for it, and then provides this data over the five bit wide data path.
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LMH0040, LMH0050 LMH0070, LMH0340 SNLS271I – APRIL 2007 – REVISED APRIL 2013 www.ti.com LVDS DATA ORDER When serializing the data, the data bit latched in on TX0 is output first, followed by TX1, TX2, TX3 and then TX4. If starting with a 10 bit word, T0..
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LMH0040, LMH0050 LMH0070, LMH0340 www.ti.com SNLS271I – APRIL 2007 – REVISED APRIL 2013 TXOUT+ TXOUT2.5V 2.5V 24 mA Figure 6. Simplified SDI Output Circuit Care must be taken in the layout of the output circuitry to meet SMPTE return loss specifications as any parasitic impedances or transmission line discontinuities will result in reflections which will adversely affect the output return loss.
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LMH0040, LMH0050 LMH0070, LMH0340 SNLS271I – APRIL 2007 – REVISED APRIL 2013 www.ti.com CML Output Interfacing The LMH0050 does not include the internal SMPTE cable driver, as its outputs are CML, include internal 50 Ω pull up resistors, and are intended to drive 100 Ω transmission lines. The LMH0050 outputs may either be connected to a differential transmission medium such as twisted pair cable, or used to drive an external cable driver.
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LMH0040, LMH0050 LMH0070, LMH0340 www.ti.com SNLS271I – APRIL 2007 – REVISED APRIL 2013 To read the data value from a register, first the host writes the device address with the LSB set to a ‘0’ denoting a write, and then the register address is written to the device. The host then reasserts the START condition, and writes the device address once again, but this time with the LSB set to a ‘1’ denoting a read, and following this the SER will drive the SDA line with the data from the addressed register.
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LMH0040, LMH0050 LMH0070, LMH0340 SNLS271I – APRIL 2007 – REVISED APRIL 2013 www.ti.com SMBus Device SMBus Device SMBus Device 3V3 3V3 SMB_CS SDA SCK SMB_CS 3V3 SDA SMB_CS SDA LVCMOS GPIO SMBus Interface SCK 3V3 SCK FPGA Host Figure 11. SMBus Configuration 3 — Host to multiple devices with multiple SMBus Interfaces GENERAL PURPOSE I/O PINS GPIO[2:0] The SER has three pins which can be configured to provide direct access to certain register values via a dedicated pin.
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LMH0040, LMH0050 LMH0070, LMH0340 www.ti.com SNLS271I – APRIL 2007 – REVISED APRIL 2013 Allow the monitoring of an external signal via the SMBus Serializer Clock output Bits 2 and 3 are used to determine the status of the internal pullup/pulldown resistors on the device—they are loaded according to the following truth table: 00: pullup and pulldown disabled 01: pulldown enabled 10: pullup enabled 11: Reserved Bit 1 is used to enable or disable the input buffer.
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LMH0040, LMH0050 LMH0070, LMH0340 SNLS271I – APRIL 2007 – REVISED APRIL 2013 www.ti.com APPLICATION INFORMATION PCB RECOMMENDATIONS The SMPTE Serial specifications have very stringent requirements for output return loss on drivers. The output return loss will be degraded by non-idealities in the connection between the SER (all variants with the exception of the LMH0050) and the output connector.
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LMH0040, LMH0050 LMH0070, LMH0340 www.ti.com SNLS271I – APRIL 2007 – REVISED APRIL 2013 The PLL loop filter is external for the SER. A capacitor is connected in series to a resistor between the LF_CP and LF_REF pins. Typical values are 500 Ω and 0.1 µF. There are several configuration pins that requiring setting to the proper level. The RSVD_H pins should be pulled High to the 3.3V rail with a 5 kΩ resistor. Depending upon the application the DVB_ASI pin may be tied off or driven.
PAGE 18
LMH0040, LMH0050 LMH0070, LMH0340 SNLS271I – APRIL 2007 – REVISED APRIL 2013 www.ti.com The TX interface between the host FPGA and the SER is composed of a 5-bit LVDS Data bus and its LVDS clock. This is a point-to-point interface and the SER includes on-chip 100 terminations. Pairs should be of equal length to minimize any skew impact. The LVDS clock (TXCLK) uses both edges to transfer the data. An SMBus is also connected from the host FPGA to the SER.
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LMH0040, LMH0050 LMH0070, LMH0340 www.ti.com SNLS271I – APRIL 2007 – REVISED APRIL 2013 3.3V 2.5V All Bypass CAPS not shown 3.3V 5 k: DAP,8,9,10,12,13, 21,22,23,24,29 GND RSVD_H 45 + TX3 46 43 + TX2 44 41 + TX1 42 39 + TX0 40 37 + TXCLK 38 - LVDS Outputs FPGA Host VDD 3V3 47 + TX4 48 - VDD 2V5 7,15,18, 2,5 25,35 1,36 TXOUT+ 17 TXOUT- 3.3V VDDPLL RSET 3.3V 3.3V LMH0050 LVCMOS GPIO SMBus Interface 1 kÖ 1 kÖ SDA 33 34 6 31 30 LF_REF LF_CP 32 SCK 100Ö TWP 16 28 22 PF 14 9.
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LMH0040, LMH0050 LMH0070, LMH0340 www.ti.com JITTER TRANSFER (dB) SNLS271I – APRIL 2007 – REVISED APRIL 2013 2 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 -22 -24 -26 1 10 100 1000 10000 100000 JITTER FREQUENCY (kHz) Figure 16. SER Jitter Transfer Function Register Descriptions Table 2 provides details on the device's configuration registers. Table 2.
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LMH0040, LMH0050 LMH0070, LMH0340 www.ti.com SNLS271I – APRIL 2007 – REVISED APRIL 2013 Table 2. SER Register Detail Table (continued) ADD 'h 03 04 05 Name Bits GPIO_1 Configuration This register configures GPIO_1. Note, if this pin is to be used as an input, then the output must be TRISTATE (bit[0]=’0’) and if used as an output, then the input buffer must be disabled (bit[1]=’0’).
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LMH0040, LMH0050 LMH0070, LMH0340 SNLS271I – APRIL 2007 – REVISED APRIL 2013 www.ti.com Table 2.
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LMH0040, LMH0050 LMH0070, LMH0340 www.ti.com SNLS271I – APRIL 2007 – REVISED APRIL 2013 Table 2. SER Register Detail Table (continued) ADD 'h Name Bits 29 LOS Status Reading the LOS status register will provide a byte which has six bits which represent the presence or absence of a signal at each of the LVDS inputs to the SER.
PAGE 24
LMH0040, LMH0050 LMH0070, LMH0340 SNLS271I – APRIL 2007 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision H (April 2013) to Revision I • 24 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 17-Apr-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LMH0040SQ/NOPB WQFN RHS 48 LMH0040SQE/NOPB WQFN RHS LMH0040SQX/NOPB WQFN RHS LMH0050SQ/NOPB WQFN LMH0050SQE/NOPB SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 48 2500 330.0 16.4 7.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMH0040SQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 LMH0040SQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0 LMH0040SQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 LMH0050SQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 LMH0050SQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0 LMH0050SQX/NOPB WQFN RHS 48 2500 367.0 367.
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MECHANICAL DATA RHS0048A SQA48A (Rev B) www.ti.
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