Datasheet

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CDR

Control

MUX

SMPTE Cable Driver

LVDS Drivers

CLK

Data

LOCK

RESET

RXCLK

RX4

RX3

RX2

RX1

RX0

SCK

SDA

SMBus

RXIN0

RXIN1

RX_MUX_SEL

TXOUT

Serial to Parallel 1:5

Bypassable 8b10b Decode

SMB_CS

GPIO[2:0]

DVB_ASI

Loopthru_EN

LMH0041, LMH0051

LMH0071, LMH0341

www.ti.com

SNLS272Q –APRIL 2007–REVISED APRIL 2013

3 Gbps, HD, SD, DVB-ASI SDI Deserializer with Loopthrough and LVDS Interface

Check for Samples: LMH0041, LMH0051, LMH0071, LMH0341

FEATURES

DESCRIPTION

The LMH0341/0041/0071/0051 SDI Deserializers are

• 5-Bit LVDS Interface

part of TI’s family of FPGA-Attach SER/DES products

• No External VCO or Clock Required

supporting 5-bit LVDS interfaces with FPGAs. When

• Reclocked Serial Loopthrough With Cable

paired with a host FPGA the LMH0341 automatically

Driver

detects the incoming data rate and decodes the raw

5-bit data words compliant to any of the following

• Powerdown Mode

standards: DVB-ASI, SMPTE 259M, SMPTE 292M,

• 3.3V SMBus Configuration Interface

or SMPTE 424M. See Table 1 for details on which

• Small 48-Pin WQFN Package

Standards are supported per device.

• Industrial Temperature range: -40°C to +85°C

The interface between the LMH0341 and the host

FPGA consists of a 5-bit wide LVDS bus, an LVDS

APPLICATIONS

clock and an SMBus interface. No external VCOs or

clocks are required. The LMH0341 CDR detects the

• SDI Interfaces for:

frequency from the incoming data stream, generates

– Video Cameras

a clean clock and transmits both clock and data to

– DVRs

the host FPGA. The LMH0341, LMH0041 and

LMH0071 include a serial reclocked loopthrough with

– Video Switchers

integrated SMPTE compliant cable driver. Refer to

– Video Editing Systems

Table 1 for a complete listing of single channel

deserializers offered in this family.

KEY SPECIFICATIONS

The FPGA-Attach SER/DES product family is

• Output compliant with SMPTE 259M-C, SMPTE

supported by a suite of IP which allows the design

292M, SMPTE 424M and DVB-ASI (See Table 1)

engineer to quickly develop video applications using

the SER/DES products. The product is packaged in a

• Typical power dissipation: 590 mW

physically small 48 pin WQFN package.

(loopthrough disabled, 3G datarate)

• 0.6 UI Minimum Input Jitter Tolerance

General Block Diagram

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2TRI-STATE is a registered trademark of National Semiconductor Corporation.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (33 pages)

PAGE 1
LMH0041, LMH0051 LMH0071, LMH0341 www.ti.com SNLS272Q – APRIL 2007 – REVISED APRIL 2013 3 Gbps, HD, SD, DVB-ASI SDI Deserializer with Loopthrough and LVDS Interface Check for Samples: LMH0041, LMH0051, LMH0071, LMH0341 FEATURES DESCRIPTION • • • The LMH0341/0041/0071/0051 SDI Deserializers are part of TI’s family of FPGA-Attach SER/DES products supporting 5-bit LVDS interfaces with FPGAs.
PAGE 2
LMH0041, LMH0051 LMH0071, LMH0341 SNLS272Q – APRIL 2007 – REVISED APRIL 2013 www.ti.
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LMH0041, LMH0051 LMH0071, LMH0341 RX4+ RX3- RX3+ RX2- RX2+ RX1- RX1+ RX0- RX0+ RXCLK- RXCLK+ SNLS272Q – APRIL 2007 – REVISED APRIL 2013 RX4- www.ti.
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LMH0041, LMH0051 LMH0071, LMH0341 SNLS272Q – APRIL 2007 – REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS Pin Name Type Description RX[4:0]+ RX[4:0]- Output, LVDS LVDS Data Output Pins Five channel wide DDR interface. RXCLK+ RXCLK- Output, LVDS LVDS Clock Output Pins DDR Interface.
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LMH0041, LMH0051 LMH0071, LMH0341 www.ti.com SNLS272Q – APRIL 2007 – REVISED APRIL 2013 Table 1.
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LMH0041, LMH0051 LMH0071, LMH0341 SNLS272Q – APRIL 2007 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) −0.3V to +4.0V Supply Voltage (VDD3V3) Supply Voltage(VDD2V5) –0.3V to +3.0V LVCMOS input voltage −0.3V to (VDD3V3+0.3V) LVCMOS output voltage −0.3V to (VDD3V3+0.
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LMH0041, LMH0051 LMH0071, LMH0341 www.ti.com SNLS272Q – APRIL 2007 – REVISED APRIL 2013 Electrical Characteristics Over supply and Operating Temperature ranges unless otherwise specified. Symbol IDD2.5 Parameter 2.5V supply current for LMH0341, LMH041, LMH0071 2.5V supply current for LMH0051 IDD3.3 3.3V supply current for LMH0341, LMH0041, LMH0071 (1) Condition Typ Max Units 2.97 Gbps LT off 67 77 mA 1.485 Gbps LT off (2) 52 59 mA 270 Mbps LT off (2) 40 46 mA 2.
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LMH0041, LMH0051 LMH0071, LMH0341 SNLS272Q – APRIL 2007 – REVISED APRIL 2013 www.ti.com SDI Input Electrical Characteristics Over supply and Operating Temperature ranges unless otherwise specified. Symbol Parameter (1) Condition Min VID Input Differential Voltage DC Coupled, VCM = 0.05V to VDD-0.05V (2) 230 IIN Input Current 0V < VIN < 2.
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LMH0041, LMH0051 LMH0071, LMH0341 www.ti.com SNLS272Q – APRIL 2007 – REVISED APRIL 2013 LVDS Switching Characteristics Over supply and Operating Temperature ranges unless otherwise specified.
PAGE 10
LMH0041, LMH0051 LMH0071, LMH0341 SNLS272Q – APRIL 2007 – REVISED APRIL 2013 www.ti.com SMBus Input Electrical Characteristics Over supply and Operating Temperature ranges unless otherwise specified.
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LMH0041, LMH0051 LMH0071, LMH0341 www.ti.com SNLS272Q – APRIL 2007 – REVISED APRIL 2013 SDI Output Switching Characteristics (LMH0341 / LMH0041 / LMH0071) Over supply and Operating Temperature ranges unless otherwise specified. Symbol Parameter (1) Condition Min SDI Output Datarate tr 270 SDI Output Rise Time SDI Output Fall Time MHz 135 ps DR=1.485 Gbps (2) 145 DR=2.
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LMH0041, LMH0051 LMH0071, LMH0341 SNLS272Q – APRIL 2007 – REVISED APRIL 2013 www.ti.com FUNCTIONAL DESCRIPTION DEVICE OPERATION The DES is used in digital video signal origination equipment. It is intended to be operated in conjunction with an FPGA host which processes data received by the SER, and converts the five bit output data to an appropriate parallel video format — usually 10 or 20 bits wide.
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LMH0041, LMH0051 LMH0071, LMH0341 www.ti.com SNLS272Q – APRIL 2007 – REVISED APRIL 2013 LVDS OUTPUT TIMING The DES output timing, in it's default condition, is described in LVDS Switching Characteristics. The user has the ability to adjust the LVDS output timing to make it easier to latch into the host FPGA if desired.
PAGE 14
LMH0041, LMH0051 LMH0071, LMH0341 SNLS272Q – APRIL 2007 – REVISED APRIL 2013 www.ti.com PLL will lose lock, and then reacquire lock. This condition can be seen by monitoring the LOCK pin where a high going pulse will indicate a loss of lock condition. If a loss of lock happens, it will be for a time period of approximately 5ms before lock is reattained. In the invent that the switch on the input is between signals at different datarates — for example from a 270 Mbps signal to a 1.
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LMH0041, LMH0051 LMH0071, LMH0341 www.ti.com SNLS272Q – APRIL 2007 – REVISED APRIL 2013 frequency λ is attenuated by 3dB, and any jitter at frequencies greater than λ is attenuated by more than this. From a design standpoint, it means that you primarily only need to worry about the jitter at frequencies below λ. The LMH0341 adjusts it's loop bandwidth dependent on datarate, so for the lower datarates, it has a lower loop bandwidth.Figure 10 shows the jitter transfer curve of an LMH0341 with a 2.
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LMH0041, LMH0051 LMH0071, LMH0341 SNLS272Q – APRIL 2007 – REVISED APRIL 2013 www.ti.com Transfer Of Data To The Device Via The SMBus During normal operation the data on SDA must be stable during the time when SCK is high. START / STOP / IDLE conditions— There are three unique states for the SMBus: START A HIGH to LOW transition on SDA while SCK is high indicates a message START condition, STOP A LOW to HIGH transition on SDA while SCK is high indicates a message STOP condition.
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LMH0041, LMH0051 LMH0071, LMH0341 www.ti.com SNLS272Q – APRIL 2007 – REVISED APRIL 2013 SMBus Device FPGA Host SMBus Device SMBus Device SMB_CS SDA SCK SMB_CS SDA SCK SMB_CS SDA LVCMOS GPIO SMBus Interface SCK 3V3 Figure 12. SMBus Configuration 2 — Host to multiple devices with SMB_CS signals SMBus Device SMBus Device SMBus Device SMB_CS SDA SCK SMB_CS SDA SMB_CS SDA LVCMOS GPIO SMBus Interface SCK 3V3 3V3 3V3 3V3 SCK FPGA Host Figure 13.
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LMH0041, LMH0051 LMH0071, LMH0341 SNLS272Q – APRIL 2007 – REVISED APRIL 2013 • • • www.ti.
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LMH0041, LMH0051 LMH0071, LMH0341 www.ti.com SNLS272Q – APRIL 2007 – REVISED APRIL 2013 APPLICATION INFORMATION PCB LAYOUT RECOMMENDATIONS In almost all applications, the inputs to the DES will be driven by the output of an equalizer such as the LMH0044. You should follow the recommendations on the equalizer datasheet for the interface between the input connector and the equalizer—the DES will be placed between the equalizer and the FPGA.
PAGE 20
LMH0041, LMH0051 LMH0071, LMH0341 SNLS272Q – APRIL 2007 – REVISED APRIL 2013 www.ti.com 0 RETURN LOSS (dB) -10 SMPTE 424 Limit -20 -30 -40 Measured Evaluation Board Return Loss -50 -60 1.00E+07 1.00E+08 1.00E+09 1.00E+10 FREQUENCY Figure 16. Evaluation Board Loopthrough Output Return Loss TYPICAL SMPTE APPLICATIONS CIRCUIT A typical application circuit for the DES is shown in Figure 17.
PAGE 21
LMH0041, LMH0051 LMH0071, LMH0341 www.ti.com SNLS272Q – APRIL 2007 – REVISED APRIL 2013 There are three supply connections (see bypass discussion in POWER SUPPLIES and also PIN DESCRIPTIONS for recommendations). The two main supplies are the 3.3V rail and the 2.5V rail. There is also a 3.3V connection for the PLL circuitry. There are multiple Ground connections for the device. The main ground connection for the SER is through the large center DAP pad.
PAGE 22
LMH0041, LMH0051 LMH0071, LMH0341 SNLS272Q – APRIL 2007 – REVISED APRIL 2013 www.ti.com 2.5V 3.3V All Bypass CAPS not shown 3.3V 5 kÖ 19 RXIN1+ 20 RXIN13.3V 22 µF 28 7.87 kÖ 14 30 nF 26 27 VDD3V3 FPGA Host 100Ö TWP LVDS Inputs 16 RXIN0+ 17 RXIN0- + 47 RX4 - 48 + 45 RX3 - 46 + 43 RX2 44 + 41 RX1 42 + 39 RX0 40 + 37 RXCLK 38 VDDPLL RSET LMH0051 3.3V 3.
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LMH0041, LMH0051 LMH0071, LMH0341 www.ti.com SNLS272Q – APRIL 2007 – REVISED APRIL 2013 REGISTER DESCRIPTIONS Table 2 provides details on the device's configuration registers. Table 2. DES Register Detail Table ADD 'h Name Bits 00 device_identificati on The seven MSBs of this register define the SMBus address for the device. The default value is 0x58h, but this may be overwritten.
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LMH0041, LMH0051 LMH0071, LMH0341 SNLS272Q – APRIL 2007 – REVISED APRIL 2013 www.ti.com Table 2.
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LMH0041, LMH0051 LMH0071, LMH0341 www.ti.com SNLS272Q – APRIL 2007 – REVISED APRIL 2013 Table 2. DES Register Detail Table (continued) ADD 'h Name Bits 22 Override This register allows the user to control the DVB_ASI and input select functions via the SMBus interface rather than the pin controls.
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LMH0041, LMH0051 LMH0071, LMH0341 SNLS272Q – APRIL 2007 – REVISED APRIL 2013 www.ti.com Table 2.
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LMH0041, LMH0051 LMH0071, LMH0341 www.ti.com SNLS272Q – APRIL 2007 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision P (April 2013) to Revision Q • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 17-Apr-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LMH0041SQ/NOPB WQFN RHS 48 LMH0041SQE/NOPB WQFN RHS LMH0041SQX/NOPB WQFN RHS LMH0051SQ/NOPB WQFN LMH0051SQE/NOPB SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 48 2500 330.0 16.4 7.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMH0041SQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 LMH0041SQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0 LMH0041SQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 LMH0051SQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 LMH0051SQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0 LMH0051SQX/NOPB WQFN RHS 48 2500 367.0 367.
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MECHANICAL DATA RHS0048A SQA48A (Rev B) www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.