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LMH1982

www.ti.com

SNLS289C –APRIL 2008–REVISED MARCH 2013

LMH1982 Multi-Rate Video Clock Generator with Genlock

Check for Samples: LMH1982

FEATURES

DESCRIPTION

The LMH1982 is a multi-rate video clock generator

• Two Simultaneous LVDS Output Clocks with

ideal for use in a wide range of 3-Gbps (3G), high-

Selectable Frequencies and Hi-Z Capability:

definition (HD), and standard-definition (SD) video

– SD Clock: 27 MHz or 67.5 MHz

applications, such as video synchronization, serial

– HD Clock: 74.25 MHz, 74.25/1.001 MHz,

digital interface (SDI) serializer and deserializer

(SerDes), video conversion, video editing, and other

148.5 MHz or 148.5/1.001 MHz

broadcast and professional video systems.

• Low-Jitter Output Clocks May Be Directly

Connected to an FPGA Serializer to Meet

The LMH1982 can generate two simultaneous SD

SMPTE SDI Jitter Specifications and HD clocks and a Top of Frame (TOF) pulse. In

genlock mode, the device's phase locked loops

• Top of Frame (TOF) Pulse with Programmable

(PLLs) can synchronize the output signals to H sync

Output Format Timing and Hi-Z Capability

and V sync input signals applied to either of the

• Two reference ports (A and B) with H and V

reference ports. The input reference can have analog

sync inputs

timing from Texas Instrument's LMH1981 multi-format

video sync separator or digital timing from an SDI

• Supports Cross-Locking of Input and Output

deserializer and should conform to the major SD and

Timing

HD standards. When a loss of reference occurs, the

• External Loop Filter Allows Control of Loop

device can default to free run operation where the

Bandwidth, Jitter Transfer, and Lock Time

output timing accuracy will be determined by the

Characteristics

external bias on the free run control voltage input.

• Free Run or Holdover Operation on Loss of

The LMH1982 can replace discrete PLLs and field-

Reference

programmable gate array (FPGA) PLLs with multiple

• User-Defined Free Run Control Voltage Input

voltage controlled crystal oscillators (VCXOs). Only

one 27.0000 MHz VCXO and loop filter are externally

• I

C Interface and Control Registers

required for genlock mode. The external loop filter as

• 3.3V and 2.5V Supplies

well as programmable PLL parameters can provide

narrow loop bandwidths to minimize jitter transfer. HD

APPLICATIONS

clock output jitter as low as 40 ps peak-to-peak can

help designers using FPGA SerDes meet stringent

• Video Genlock and Synchronization

SDI output jitter specifications.

• FPGA SDI SerDes Recovered Clock

Generation

The LMH1982 is offered in a space-saving 5 mm x 5

mm 32-pin WQFN package and provides low total

• Triple Rate 3G/HD/SD-SDI SerDes

power consumption of about 250 mW (typical).

• Video Capture, Conversion, Editing and

Distribution

• Video Displays and Projectors

• Broadcast and Professional Video Equipment

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (43 pages)

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LMH1982 www.ti.
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LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com Typical Video Genlock Block Diagram VC LOOP FILTER VCXO 27 MHz ANALOG REF. IN LMH1981 MULTI-FORMAT VIDEO SYNC SEPARATOR H sync V sync REF_A TX 27 or 67.5 MHz LMH1982 MULTI-RATE CLOCK GENERATOR H sync OPTIONAL BACK-UP REFERENCE INPUTS V sync GENLOCKED 3G-SDI OUT TOF LPF VCXO TOF SD_CLK FPGA with SerDes TRIPLE-RATE SDI HD_CLK REF_B RX_1 74.25, 74.176, 148.5 or 148.
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LMH1982 www.ti.
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LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com Pin Descriptions (1) Pin No. Pin Name I/O – DAP – Supply Die Attach Pad (Connect to GND) 1 VC_FREERUN I Analog Free Run Control Voltage Input 2, 10, 18, 22, 26, 30 GND – Supply Ground 3, 21, 27, 28, 32 VDD – Supply 3.
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LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 Operating Ratings VDD 3.3V ± 5% DVDD 2.5V ± 5% Input Voltage 0V to VDD Temperature Range, TA 0°C to 70°C Electrical Characteristics Unless otherwise specified, all limits are specified for TA = 25°C, VDD = 3.3V, DVDD = 2.5V, Boldface limits apply at the temperature extremes.
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LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (continued) Unless otherwise specified, all limits are specified for TA = 25°C, VDD = 3.3V, DVDD = 2.5V, Boldface limits apply at the temperature extremes. Parameter Test Conditions Min (1) Typ (2) Max (1) Units tR Rise Time 15 pF load 1.5 ns tF Fall Time 15 pF load 1.
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LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 Electrical Characteristics (continued) Unless otherwise specified, all limits are specified for TA = 25°C, VDD = 3.3V, DVDD = 2.5V, Boldface limits apply at the temperature extremes. Parameter Test Conditions VOS Common Signal Output Voltage (13) 100Ω differential load |VOD| |Change to VOD| for Complementary Output States (13) |VOS| Min (1) 1.125 Typ (2) 1.250 Max (1) Units 1.
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LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics Test conditions: VDD = 3.3V, DVDD = 2.5V, Genlock mode, outputs initialized. H sync and V sync signals to REF_A inputs are from the LMH1981 sync separator, which receives an analog video reference signal from a Tektronix TG700 AVG7/AWVG7 (SD/HD) video signal generator. See Note section below for register settings (in decimal): NTSC TOF Pulse PAL TOF Pulse NTSC 500 mV/DIV PAL 500 mV/DIV H sync 2.
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LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 Supported Standards and Timing Formats Table 1 lists the known supported standard timing formats and includes the relevant parameters that can be used to configure the LMH1982 for the input reference and output timing. For the related programming instructions, see sections INPUT REFERENCE and OUTPUT CLOCKS AND TOF. Table 1.
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LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com Table 1. Input Reference and Output Timing Parameters (1)(2) (continued) INPUT TIMING PARAMETERS OUTPUT TIMING PARAMETERS (2) PLL 1 Reference Divider1 (3) PLL 1 Feedback Divider PLL 1 Phase Comparison Frequency (kHz) Total Lines per Frame Counter Clock Frequency (MHz) Total Clocks per Line Counter Total Lines per Frame Counter Frame Rate (Hz) 1080i/60 1 [5] 800 [4000] 33.75 [6.75] 1125 [225] 74.25 (27.
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LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 APPLICATION INFORMATION FUNCTIONAL OVERVIEW The LMH1982 is an analog phase locked loop (PLL) clock generator that can output simultaneous SD and HD video clocks synchronized or “genlocked” to H sync and V sync input reference timing. The LMH1982 features an output Top of Frame (TOF) pulse generator with programmable timing that can also be synchronized to the reference frame.
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LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com 148.35 MHz PLL Initialization Sequence The following programming sequence is required to initialize PLL 3 and generate a correct 148.35 MHz output once it is selected as the HD_CLK; otherwise, the clock may have duty cycle errors, frequency errors, and/or high jitter. This PLL initialization sequence must be programmed after switching from another HD clock frequency or Hi-Z mode, as well as after a device reset or power cycle condition.
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LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 Evaluating the LMH1982 For information about SDI jitter performance using the LMH1982 with the LMH1981 sync separator, please refer to the following application notes: • AN-1893: Demonstrating SMPTE-compliant SDI Output Jitter using the LMH1982 and Virtex-5 GTP Transmitter (SNLA110) • AN-1841: LMH1982 Evaluation Board User Guide (SNVA343) The LMH1982SQEEVAL Evaluation Board can be ordered from Texas Instrument's website.
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LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com Genlock Mode State Diagram Figure 7 shows the Genlock mode state diagram for different input reference and PLL lock conditions. It also includes Free Run and Holdover states for the loss of reference operation, specified by the HOLDOVER bit (register 00h). Each state indicates the NO_REF and NO_LOCK status flag output conditions. Reference & lock lost FREE RUN NO_REF = 1 NO_LOCK = 1 Reg.
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LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 The output frequency accuracy will degrade as the VCXO accuracy drifts with the decaying control voltage. Moreover, because the H_ERROR setting (register 00h) affects the reference error threshold for LOR indication, a higher setting for H_ERROR may result in reduced output accuracy upon LOR indication compared to when H_ERROR = 0. For more information on programming H_ERROR, see section Programming the Loss of Reference (LOR) Threshold.
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LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com Some supported input formats in Table 1 have two sets of compatible divider values: reduced dividers and nonreduced dividers. See Examples 2A and 2B below. Because the loop response of PLL 1 is dependent on the feedback divider value, a lower loop bandwidth and phase comparison frequency can be achieved by programming the non-reduced divider set (see LOOP RESPONSE ). Examples: 1) For 1080i/59.
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LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 Table 4. SD Clock Frequency Selection SD_CLK (MHz) SD_FREQ Register 08h PLL# 27 0 1 67.5 1 4 The HD clock frequency can be selected from Table 5 and programmed to HD_FREQ (register 08h). PLL 2 and PLL 3 are used to generate the four different HD clock rates but only one HD clock can be selected at a time. If the HD_CLK output is not needed, it can be put in Hi-Z mode by setting HD_HIZ = 1 (register 08h). NOTE If 148.
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LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.
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LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 Output TOF Clock The TOF pulse is derived from a counter chain, which receives either output clock (SD_CLK or HD_CLK) from a 2:1 MUX block, as shown in Figure 9. The TOF clock from the MUX can be selected by programming TOF_CLK (register 0Ch). To select SD_CLK as the TOF clock, set TOF_CLK = 0; otherwise, set TOF_CLK = 1 to select HD_CLK. The selected TOF clock frequency is determined by the SD_FREQ or HD_FREQ register setting.
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LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 • www.ti.com TOF_LPFM = 1125 (5) Option 2) 1080p/59.94 TOF generation using 27 MHz TOF rate = 27 MHz / 2002 x 225) = 60/1.001 Hz where • • • fTOF_CLK = 27 MHz (TOF_CLK = 0, SD_FREQ = 0) TOF_PPL = 2002 TOF_LPFM = 225 (6) As an example, Figure 10 shows a timing illustration for 1080p/59 TOF and clock outputs for .
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LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 Example: If the input reference is 525i with a frame rate of 30/1.001 Hz and the output format is 625i with a frame rate of 25 Hz, then: Frame rate ratio = (30/1.001) / 25 = 1200 / 1001 Therefore, the numerator, 1200, should be programmed to TOF_RST.
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LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com To ensure that the output clock and TOF pulse are properly aligned and subsequently phase locked to the reference frame, the output initialization sequence should be programmed accordingly. During the output frame immediately prior to the frame the initialization is to occur: 1. Set EN_TOF_RST = 1(register 0Ah) to enable output alignment mode. 2. Toggle TOF_INIT (register 0Ah) from 0 to 1 to reset the internal counters.
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LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 Reference Detection In Genlock mode, a valid reference will be indicated by NO_REF = 0 when all the criteria below are met. Otherwise, a loss of reference (LOR) will be indicated by NO_REF = 1. • An H sync signal is applied to the input reference and conforms to one of the standard formats in Table 1. A V sync signal is not used in reference detection. • The PLL divide registers are programmed according to the input reference format.
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LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com A larger value for LOCK_CTRL will yield shorter lock indication time (although not actual lock time) at the expense of higher output phase error when lock is initially indicated, whereas a smaller value will yield the opposite effect.
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LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 The -3 dB loop bandwidth, BW, can be approximated by: BW = ICP1 * RS * KVCO / FB_DIV where (9) ICP1 = Nominal VCXO PLL charge pump current (in amps) programmed by setting ICP1 (register 13h). For example: ICP1 = 250 µA: ICP1 = 08h (default value) ICP1 = 0 µA: ICP1 = 00h (min) ICP1 = 62.5 µA; ICP1 = 02h (practical min) ICP1 = 968.75 µA; ICP1 = 1Fh (max) ICP1 step size = 31.
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LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com Loop Response Optimization Tips The need to support various input reference formats will usually require a diverse range of PLL divider values, which can each yield a different loop response assuming all other PLL parameters are kept the same. Typically, it is desired to design and optimize the loop response across all supported input formats without modification to the loop filter circuit.
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LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 I2C INTERFACE PROTOCOL The protocol of the I2C interface begins with the start pulse followed by a byte comprised of a seven-bit slave device address and a read/write bit as the LSB. Therefore, the address of the LMH1982 for write sequences is DCh (1101 1100) and the address for read sequences is DDh (1101 1101). Figure 12, Figure 13, and Figure 14 show a write and read sequence across the I2C interface.
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LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com SCL SDA D7 S t a r t 1 1 0 1 1 1 0 2 I C Slave Address $DD 1 0 R e a d A C K D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 A C K Data Byte 1 Data Byte n A C K S t o p Figure 14. LMH1982 Read Sequence – Data Read Transfer I2C Enable Control Pin When the active low input I2C_ENABLE = 0, the LMH1982 will enable I2C communication via its fixed slave address; otherwise, the LMH1982 will not respond.
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LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 Genlock And Input Reference Control Registers Register 00h Bits 2-0: H Input Error Max Count (H_ERROR) The H_ERROR bits control the reference detector's error threshold, which determines the maximum number of missing H sync pulses before indicating a LOR. See section Programming the Loss of Reference (LOR) Threshold. Bit 3: Holdover on Loss of Reference (HOLDOVER) The HOLDOVER bit controls the operating mode when a loss of reference occurs.
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LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com In Free Run mode, REF_VALID will be set to 0 to indicate the absence of any input pulses at the selected HREF port. Bit 1: SD Clock PLL Lock Status (SD_LOCK) SD_LOCK is a read-only bit and indicates PLL lock status of the selected SD clock. See section PLL Lock Detection. SD_LOCK = 0: Indicates loss of lock. SD_LOCK = 1: Indicates valid lock.
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LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 27M_REF = 1: 27 MHz clock input signal. Also, set REF_DIV_SEL =1 and FB_DIV = 1 NOTE Because the loop gain, K, for 27 MHz clock input is much larger than for an H sync input (due to the large difference in FB_DIV), the loop filter design will be necessarily different between the 27 MHz input and H sync inputs. Alternatively, it's possible to use an external counter circuit to divide the 27 MHz clock to a lower frequency (e.g.
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LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com PLL 4 Charge Pump Current Control Register Register 06h Bits 3-0: Charge Pump Current Control for PLL 4 (ICP4) ICP4 can be programmed to specify charge pump current for PLL 4, which generates the 67.5 MHz SD clock. NOTE Bit 3 is inverted internally, so the default ICP4 value of 0000b (0h) actually yields an effective value of 1000b (8h), which is the mid-scale setting. The PLL 4 charge pump current increases linearly with the effective value.
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LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 Bit 4: HD Clock Output Mode (HD_HIZ) Set the HD_HIZ bit to 1 to put the HD_CLK output pair in high-impedance (Hi-Z) mode; otherwise, the HD_CLK output will be enabled. Bit 5: Top of Frame Output Mode (TOF_HIZ) Set the TOF_HIZ bit to 1 to put the TOF output pin in high-impedance (Hi-Z) mode; otherwise, the output will be enabled. Bits 7-6: Reserved (RSV) These RSV bits are reserved.
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LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com This bit should be programmed to select the output TOF clock reference according to the desired output format. The selected TOF clock frequency is used in specifying the output frame rate. Any output format, including HD, can use 27 MHz as the TOF clock to generate its TOF pulse by programming the output counter values corresponding to the 27 MHz SD clock as shown in Table 1. See sections Output TOF Clock and Output Frame Timing.
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LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 To minimize lock time, using a large or maximum ICP1 can result in faster PLL settling time due to a wider loop bandwidth. Once phase lock has been achieved, using a lower ICP1 (that yields sufficient stability) can provide good input jitter rejection due to a narrower loop bandwidth; this can be helpful to minimize low-frequency input jitter from being transferred to the output clocks.
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LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com TYPICAL SYSTEM BLOCK DIAGRAMS LOOP FILTER VC VCXO 27 MHz ANALOG REF. IN LMH1981 MULTI-FORMAT VIDEO SYNC SEPARATOR H sync V sync REF_A TX 27 or 67.5 MHz LMH1982 MULTI-RATE CLOCK GENERATOR H sync OPTIONAL BACK-UP REFERENCE INPUTS V sync GENLOCKED 3G-SDI OUT TOF LPF VCXO TOF SD_CLK FPGA with SerDes TRIPLE-RATE SDI HD_CLK REF_B RX_1 74.25, 74.176, 148.5 or 148.
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LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 VC LOOP FILTER VCXO 27 MHz H sync UNUSED INPUTS V sync REF_A LPF VCXO TOF SD_CLK LMH1982 MULTI-RATE CLOCK GENERATOR LOOPED 3G-SDI OUT TOF TX 27 or 67.5 MHz FPGA with SerDes TRIPLE-RATE SDI H sync V sync 3G-SDI IN HD_CLK REF_B RX_1 74.25, 74.176, 148.5 or 148.35 MHz RECOVERED SYNC TIMING FROM 3G-SDI IN Figure 17. Triple-Rate SDI Loop-through LOOP FILTER VC VCXO 27 MHz ANALOG REF.
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LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision B (March 2013) to Revision C • 38 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 21-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LMH1982SQ/NOPB WQFN RTV 32 LMH1982SQE/NOPB WQFN RTV LMH1982SQX/NOPB WQFN RTV SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 32 250 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 32 4500 330.0 12.4 5.3 5.3 1.3 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 21-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMH1982SQ/NOPB WQFN RTV 32 1000 210.0 185.0 35.0 LMH1982SQE/NOPB WQFN RTV 32 250 210.0 185.0 35.0 LMH1982SQX/NOPB WQFN RTV 32 4500 367.0 367.0 35.
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MECHANICAL DATA RTV0032A SQA32A (Rev B) www.ti.
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