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LMH1982 Evaluation Board

USB Board

USB

Node

COP8

USB Current

Sense

USB

Cable

USB 5V

LDOs

LMH1981

LMH1982

Ref. In

USB

SD_CLK

HD_CLK

I/O

signals

Ext.

H/V In

3.3V and 2.5V

LPF+VCXO

User's Guide

SNOA527A–May 2008–Revised April 2013

AN-1841 LMH1982 Evaluation Board

1 Introduction

The LMH1982 evaluation board was designed by Texas Instruments to evaluate the performance and

operation of the LMH1982 multi-rate video clock and timing generator with the LMH1981 SD/HD video

sync separator. The evaluation board provides input ports to receive analog or digital reference signals,

SMA connector ports to transmit the differential output clocks, and headers to access various input/output

signals. On-board toggle switches allow control over the sync inputs and control inputs, such as device

reset. A USB interface board is also provided to allow programming of the LMH1982 through a PC's USB

port using TI's LMH1982 evaluation software.

Refer to the Evaluation Board Schematic, PCB Layout, and Bill of Materials sections, as well as the

collateral listed in the References section.

1.1 USB Interface Board

Headers X2 and X4 of the USB interface board should be plugged into headers J7 and J11 of the

evaluation board. The USB board's firmware supports the I

C interface, which enables the user to program

the LMH1982 from a PC running the evaluation software. The USB board can also provide 5V from the

PC's USB port to power the LDO regulators on the evaluation board. The block diagram in Figure 1 shows

the connections between the PC, USB board, and evaluation board.

Figure 1. Simplified Block Diagram of the Evaluation Setup

1.2 Power Supplies

The evaluation board requires a 5V supply and ground connection to power the on-board LP38693 LDO

regulators (U1, U2).

To use 5V from the USB port via header J7, shunt pins 1 and 2 of jumper JP3. Refer to Table 1 for the pin

assignment of JP3. If the USB supply is used, make sure that the USB port of the PC is capable of

nominally sourcing 150 mA (0.75W at 5V). When powering the evaluation board, the USB supply voltage

should measure 5V ± 5% at pin 4 of J7.

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SNOA527A–May 2008–Revised April 2013 AN-1841 LMH1982 Evaluation Board

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Summary of content (14 pages)

PAGE 1
User's Guide SNOA527A – May 2008 – Revised April 2013 AN-1841 LMH1982 Evaluation Board 1 Introduction The LMH1982 evaluation board was designed by Texas Instruments to evaluate the performance and operation of the LMH1982 multi-rate video clock and timing generator with the LMH1981 SD/HD video sync separator.
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Introduction www.ti.com To use an external 5V supply, shunt pins 2 and 3 of JP3 and connect the supply leads to pins 1 and 2 of header J1. Table 1. 5V Select Jumper, JP3 Pin #, Location Pin Name 1, Left EXT 5V 2, Center INPUT 5V 3, Right USB 5V The LP38693 LDO regulators provide clean 3.3V and 2.5V for the evaluation board. If needed, it is possible to bypass the LDOs and apply external 3.3V and 2.5V supplies to the appropriate pins of J1. See Table 2 for the pin assignments of J1.
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Introduction www.ti.com Table 3. Input Select Switch, SW2 ON OFF • U7 buffer output is in Hi-Z mode • LMH1981 sync signals is gated off from port REF_A • External input signals can be applied to HIN_A and VIN_A of header J8 1.3.2 • U7 buffer output is enabled • LMH1981 sync signals are passed to port REF_A Digital Reference Input In addition to the analog timing signals from the sync separator, external H and V sync input signals can be applied to ports REF_A or REF_B via header J8.
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Introduction 1.6 www.ti.com 27 MHZ VCXO and Loop Filter The LMH1982 requires an external 27 MHz VCXO (X1) and loop filter circuitry for operation of the VCXO PLL. The board is populated with a CTS 357-series 27.0000 MHz VCXO with ±50 ppm absolute pull range (APR), which yields 1000 Hz/V nominal tuning sensitivity (KVCO). The VCXO input control voltage can be measured at test point TP21. The second-order loop filter consists of RS = 20 kΩ (R8), CS = 44 μF (C10 = C27 = 22 μF), and CP = 1 μF (C28).
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Introduction www.ti.com 1.7 Free Run Control Voltage Input The LMH1982 provides the option to set the VCXO's free run control voltage by external biasing of the VC_FREERUN input (pin 1). The analog bias voltage applied to the VC_FREERUN input will be internally connected to the LPF output (pin 31) though a low impedance switch when the LMH1982 is operating in free run.
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Introduction www.ti.com Table 8. Genlock Status LEDs Condition 1.10 D3 (NO_LOCK) D4 (NO_REF) Genlock mode Reference lost PLL(s) not locked OFF OFF Genlock mode Reference valid PLL(s) locking OFF ON Genlock mode Reference valid PLLs locked ON ON I2C Interface The I2C interface clock (SCL) and data (SDA) signals come from the USB board via header J11. These signals can be probed at test points TP11 (SCL) and TP12 (SDA). Both signals traces have 4.
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Evaluation Board Schematic www.ti.com 2 Evaluation Board Schematic VCC3V3 VDD R3 C9 100 nF TP3 VDD C41 47 PF 0 + C42 10 PF C5 100 nF C13 100 nF EXT3V3 U1 LP38693MP-3.
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Evaluation Board Schematic www.ti.com U3 REXT 1 2 C33 100 nF VCC VIN 3 4 5 Rext OEOUT GND BPOUT Vcc CSOUT Vin VSOUT SD/HD HSOUT 10 OEOUT U4 LMH1981 9 REXT 8 R1 7 VSOUT 6 HSOUT 1 Rext OEOUT 14 OEOUT TP7 OEOUT R26 50 10.
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Evaluation Board Schematic www.ti.com SW2 VCC 1 6 2 C38 SWITCH 1 2 3 4 1 8 2 7 J8 3 6 4X2 4 5 8 HREF A 7 VREF A 6 HREF B R18 VCC VCC OE1 10 PF C19 8 33k 100 nF HSYNC 2 VREF A 3 A1 OE2 7 VCC VCC R30 5 1 U7 VREF B Y2 Y1 6 HREF A 5 VSYNC NP (10k) R29 NP (10k) 4 GND A2 NC7WZ125K8X R20 NP (0) R21 NP (0) Figure 5.
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Evaluation Board Schematic www.ti.
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Evaluation Board Layout www.ti.com 3 Evaluation Board Layout Figure 7.
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Evaluation Board Bill of Materials www.ti.com Figure 8.
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References www.ti.com Qty Part Designator Part Footprint 4 J3, J4, J5, J6 EDGE MOUNT SMA SMA 2 J7, J11 0.100" 16 PIN HEADER 8516-4500PL 3 J8, J9, J10 4X2 HEADER 4X2 4 JP1, JP2, JP4, JP8 2 PIN HEADER 2X1 1 JP3 3 PIN HEADER 3X1 1 P1 50K SMT POT ST4ETA503CT-ND 7 R1, R29, R30, R31, R32, R33, R34 10.0K 1% 0603 9 R2, R4, R11, R12, R19, C31, C34, C35, C37 0 0603 3 R3, R15, R22 0 0805 1 R5 2.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.