Datasheet

U7
8
A2
5
1
1
8
8
2
2
7
7
3
3
6
6
4
4
5
5
HREF A
VREF B
J8
OE1
VCC
1
R18
33k
VCC
A1
2
HSYNC
Y2
3
GND
4
VCC
R30
NP (10k)
VREF A
VCC
R29
NP (10k)
HREF A
VSYNC
NC7WZ125K8X
R20
NP (0)
R21
NP (0)
Y1
6
OE2
7
C19
100 nF
C38
10 PF
VCC
HREF B
VREF A
2
1
6
SW2
SWITCH
4X2
www.ti.com Evaluation Board Schematic
Figure 5. Schematic (3 of 4)
Input Header and Switch-Controlled Logic Buffer
9
SNOA527A–May 2008–Revised April 2013 AN-1841 LMH1982 Evaluation Board
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