Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - Video editing Clock generator LLP 40 EP (6x6)

LOOP

FILTER

27 MHz

VCXO

LMH1983

FPGA

A/V Frame Sync with

Downconverter,

Audio Embedder and

De-embedder

1080p/59.94 SDI out

+ embedded audio

LMH1981

Sync

Separator

H sync

V sync

525i

Analog

ref. in

F sync

27 MHz (PLL1)

148.5 MHz (PLL2)

148.35 MHz (PLL3)

24.576 MHz (PLL4)

1080p/59.94 SDI in

+ embedded audio

Genlocked to video ref. in

525i/29.97 SDI out

+ embedded audio

CLKout1

CLKout4

CLKout2

CLKout3

Hin

Vin

Fin

29.97 Hz (TOF1)

29.97 Hz (TOF2)

59.94 Hz (TOF3)

5.994 Hz

LMH1983

www.ti.com

SNLS309G –APRIL 2010–REVISED JANUARY 2011

LMH1983 3G/HD/SD Video Clock Generator with Audio Clock

Check for Samples: LMH1983

FEATURES

APPLICATIONS

• Four PLLs for Simultaneous A/V Clock

• Triple Rate (3G/HD/SD) SDI SerDes

Generation

• FPGA Reference Clock Generation/Cleaning

– PLL1: 27 or 13.5 MHz

• Audio Embed/De-embed

– PLL2: 148.5 or 74.25 MHz

• Video Cameras

– PLL3: 148.5/1.001 or 74.25/1.001 MHz

• Frame Synchronizers (Genlock, DARS)

– PLL4: 98.304 MHz / 2

(X = 0 to 15)

• A-D/D-A Conversion, Editing, Processing

• 3 x 2 Video Clock Crosspoint Cards

• Flexible PLL Bandwidth to Optimize Jitter • Keyers and Logo Inserters

Performance and Lock Time

• Format/Standards Converters

• Soft Re-synchronization to New Reference

• Video Displays and Projectors

• Digital Holdover or Free-run on Loss of

• A/V Test and Measurement Equipment

Reference

• Status Flags for Loss of Reference and Loss

of PLL Lock

• 3.3V Single Supply Operation

• I

C Interface With Address Select Pin (3 states)

DESCRIPTION

The LMH1983 is a highly-integrated programmable audio/video (A/V) clock generator intended for broadcast and

professional applications. It can replace multiple PLLs and VCXOs used in applications supporting SMPTE serial

digital video (SDI) and digital audio AES3/EBU standards. It offers low-jitter reference clocks for any SDI

transmitter to meet stringent output jitter specifications without additional clock cleaning circuits.

The LMH1983 features automatic input format detection, simple programming of multiple A/V output formats,

genlock or digital free-run modes, and override programmability of various automatic functions. The recognized

input formats include HVF syncs for the major video standards, 27 MHz, 10 MHz, and 32/44.1/48/96 kHz audio

word clocks.

TYPICAL APPLICATION – VIDEO GENLOCK TIMING GENERATION for A/V FRAME

SYNCHRONIZER

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (38 pages)

PAGE 1
LMH1983 www.ti.com SNLS309G – APRIL 2010 – REVISED JANUARY 2011 LMH1983 3G/HD/SD Video Clock Generator with Audio Clock Check for Samples: LMH1983 FEATURES APPLICATIONS • • • • • • • 1 2 • • • • • • • Four PLLs for Simultaneous A/V Clock Generation – PLL1: 27 or 13.5 MHz – PLL2: 148.5 or 74.25 MHz – PLL3: 148.5/1.001 or 74.25/1.001 MHz – PLL4: 98.
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LMH1983 SNLS309G – APRIL 2010 – REVISED JANUARY 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The dual-stage PLL architecture integrates four PLLs with three on-chip VCOs.
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LMH1983 www.ti.
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LMH1983 SNLS309G – APRIL 2010 – REVISED JANUARY 2011 www.ti.com PIN DESCRIPTIONS (continued) Pin No. Pin Name I/O Signal Level 12 NO_ALIGN O LVCMOS Loss of alignment status flag for OUTs 1–4 (active high) 13 NO_REF O LVCMOS Loss of reference status flag (active high) 14 15 CLKout4– CLKout4+ O LVDS Audio clock from PLL4 (fundamental rate is 98.304 MHz). The output is 24.576 MHz by default and is selectable via the host. 3.
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LMH1983 www.ti.com SNLS309G – APRIL 2010 – REVISED JANUARY 2011 ABSOLUTE MAXIMUM RATINGS (1) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and specifications. ESD Tolerance (2) Human Body Model 2500V Machine Model 250V Charge-Device Model 750V Supply Voltage, VDD 3.6V Input Voltage (any input) −0.3V to VDD +0.3V Output Voltage (any output) −0.3V to VDD +0.
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LMH1983 SNLS309G – APRIL 2010 – REVISED JANUARY 2011 www.ti.com ELECTRICAL CHARACTERISTICS(1)(2) (continued) Unless otherwise specified, all limits are specified for TA = 25°C, VDD = 3.3V, RL_CLK = 100Ω (CLKout differential load). Boldface limits apply at the temperature extremes. Symbol Parameter Min (3) Conditions Typ (4) Max (3) Units Status Flag Outputs (NO_REF, NO_ALIGN,NO_LOCK) VOL Low Output Voltage IOUT = +10 mA VOH High Output Voltage IOUT = −10 mA 0.4 VDD−0.
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LMH1983 www.ti.com SNLS309G – APRIL 2010 – REVISED JANUARY 2011 ELECTRICAL CHARACTERISTICS(1)(2) (continued) Unless otherwise specified, all limits are specified for TA = 25°C, VDD = 3.3V, RL_CLK = 100Ω (CLKout differential load). Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (3) Typ (4) Max (3) Units 1.125 1.25 1.
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LMH1983 SNLS309G – APRIL 2010 – REVISED JANUARY 2011 www.ti.com Table 1. Supported Formats Lookup Table (LUT) INPUT TIMING / PLL1 PARAMETERS 8 OUTPUT TIMING (OUT1–4) PARAMETERS Format Reference Divider Feedback Divider Phase Detector (PD) Freq. (kHz) PD Periods per Frame Counter NTSC, 525i 1 1716 15.7343 525 PAL, 625i 1 1728 15.625 625 525p 1 858 31.4685 525 625p 1 864 31.25 625 720p/60 1 600 45.0 720p/59.94 5 3003 720p/50 1 720 720p/30 1 720p/29.
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LMH1983 www.ti.com SNLS309G – APRIL 2010 – REVISED JANUARY 2011 AUTO FORMAT DETECTION CODES The Auto Format Detection Codes apply to registers 0x07 (Output Mode – PLL2 Format), 0x08 (Output Mode – PLL3 Format) and 0x20 (Input Format). Format Code Description Hsync Period (in 27 MHz clocks) Interlaced (I) / Progressive (P) 0 480i/29.97 1716 I 1 576I25 1728 I 2 480P59.94 858 P 3 576P50 864 P 4 720P60 600 P 5 720P59.94 600.6 P 6 720P50 720 P 7 720P30 1200 P 8 720P27.
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LMH1983 SNLS309G – APRIL 2010 – REVISED JANUARY 2011 www.ti.com Table 2.
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LMH1983 www.ti.com SNLS309G – APRIL 2010 – REVISED JANUARY 2011 Table 2. Register Map (continued) ADD Name Bits Field 0x06 Input Polarity 7:4 RSVD R/W Default Description 3 EN_AUTOPOL R/W 1 Enables Auto Polarity Detection and Correction. The proper polarity needs to be set to synchronize the output timing signals to the leading edges of the H and V inputs. 0 = The polarities of HVF inputs are manually set by their respective polarity override registers.
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LMH1983 SNLS309G – APRIL 2010 – REVISED JANUARY 2011 www.ti.com Table 2. Register Map (continued) ADD Name Bits Field R/W Default Description 5:4 TOF1_Align_Mode R/W 11 00 = Auto-align when misaligned 01 = Reserved 10 = Always Align 11 = Never Align NOTE: When H_ONLY is 1, TOF1 align mode is forced to never align.
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LMH1983 www.ti.com SNLS309G – APRIL 2010 – REVISED JANUARY 2011 Table 2. Register Map (continued) ADD Name Bits Field 0x14 Alignment Control – AFS 7:6 RSVD R/W Default Description 5:4 AFS_Align_Mode R/W 11 00 = auto align when misaligned 01 = one shot manual align. AFS_Init_Input reg determines if done by pin (INIT) or register (AFS_INIT = 1) 10 = always align 11= never align 3 AFS_Init_Input R/W 0 0 = Rising edges on INIT (pin 6) trigger AFS one shot manual align.
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LMH1983 SNLS309G – APRIL 2010 – REVISED JANUARY 2011 www.ti.com Table 2. Register Map (continued) ADD Name Bits Field 0x1C Loss of Lock Threshold 7:5 RSVD 4:0 0x1D Mask Control – PLL Lock and Output Align R/W Default Description LOCK1_Threshold R/W 10000 Sets the number of Hsync periods to wait before setting loss of lock. Since during blanking there can have up to 5 missing Hsync pulses, this value is usually set > 6.
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LMH1983 www.ti.com SNLS309G – APRIL 2010 – REVISED JANUARY 2011 Table 2. Register Map (continued) ADD Name Bits Field 0x26 PLL1 Advanced Control FastLock Delay 7:4 RSVD R/W Default Description 3:0 FastLock Delay R/W 0000 Sets the amount of time that PLL1_Lock must be asserted before the PLL1 Charge pump current is reduced from the ICP1_Fast value to the ICP1 value. The time delay is specified in units of half seconds. Delay = FastlockDelay*0.5 Seconds. Valid values are from 0 to 10.
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LMH1983 SNLS309G – APRIL 2010 – REVISED JANUARY 2011 www.ti.com Table 2. Register Map (continued) ADD Name Bits Field R/W Default Description 0x38 PLL4 Advanced Control N counter LSB 7:0 DIV_N4_LSB R/W 0x00 8 LSBs of the N divider in PLL4 0x39 PLL4 Advanced Control VCO Range 7:0 VCO4 Range R/W 0x16 The value in the VCO4 Range register is used to adjust the center frequency of PLL4.
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LMH1983 www.ti.com SNLS309G – APRIL 2010 – REVISED JANUARY 2011 Table 2. Register Map (continued) ADD Name Bits Field 0x55 User Auto Format R divider MSB 7:2 RSVD R/W Default Description 1:0 USR_DIV_R1_MSB R/W 00 0x56 User Auto Format R Divider LSB See Applications Information section for details. 7:0 USR_DIV_R1_LSB R/W 0x00 See Applications Information section for details.
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LMH1983 SNLS309G – APRIL 2010 – REVISED JANUARY 2011 www.ti.com Table 3.
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LMH1983 www.ti.com SNLS309G – APRIL 2010 – REVISED JANUARY 2011 APPLICATION INFORMATION FUNCTIONAL OVERVIEW The LMH1983 is an analog phase locked loop (PLL) clock generator that can output simultaneous clocks at any of a variety of video and audio rates, synchronized or “genlocked” to H sync and V sync input reference timing. The LMH1983 features an output Top of Frame (TOF) pulse generator for each of its four channels, each with programmable timing that can also be synchronized to the reference frame.
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LMH1983 SNLS309G – APRIL 2010 – REVISED JANUARY 2011 www.ti.com READ SEQUENCE Read Sequences are made up of two I2C transfers. The first is the address access transfer, which consists of a write sequence that transfers only the address to be accessed. The second is the data read transfer which starts at the address indicated in the first transfer, and increments to the next address, continuing to read addresses until a stop condition is encountered.
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LMH1983 www.ti.com SNLS309G – APRIL 2010 – REVISED JANUARY 2011 REFERENCE DETECTION The default mode for the device is to use 'Auto Format Detect' in which the device determines the reference format from among those shown in the Auto Format Detection Code table, and sets up the internal configurations accordingly. There are 31 pre-defined formats, plus one format that the user can define which will be recognized.
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LMH1983 SNLS309G – APRIL 2010 – REVISED JANUARY 2011 www.ti.com Under normal operation, several of these parameters are set by the device automatically, for example the charge pump current and the value of 'FB_DIV'. When the input reference format changes, both N and the charge pump current are updated, N is changed to allow for lock to the new reference, and the charge pump current is adjusted to try to maintain constant loop bandwidth.
PAGE 23
LMH1983 www.ti.com SNLS309G – APRIL 2010 – REVISED JANUARY 2011 LOOP FILTER CAPACITORS The most common types of capacitors used in many circuits today are ferroelectric ceramic capacitors such as X7R, Y5V, X5R. Y5U, etc. These capacitors suffer from piezoelectric effects, which generate an electrical signal in response to mechanical vibration, stress and shock. This effect can adversely affect the jitter performance when presented to the control input to the VCXO.
PAGE 24
LMH1983 SNLS309G – APRIL 2010 – REVISED JANUARY 2011 www.ti.com Separate from the time that it takes for the PLL to lock, there is a circuit which determines how to set the NOLOCK output pin. The LMH1983 PLL operates by adjusting the voltage that is applied to the VCXO control pin to lock the VCXO to a harmonic of the incoming reference.
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LMH1983 www.ti.com SNLS309G – APRIL 2010 – REVISED JANUARY 2011 The third mode is holdover mode. In the event that the reference is lost, there is an A/D — D/A pair which is able to take over for the PLL control loop, and hold the VCXO control voltage constant. For this to work properly, the device has to realize that it has lost its reference shortly after the reference is indeed lost.
PAGE 26
LMH1983 SNLS309G – APRIL 2010 – REVISED JANUARY 2011 27 MHz In www.ti.com Phase/ Frequency Detector ÷R ÷ (N x 8) ÷2 PLL4_DIV CLKout4 TOF4_ACLK MUX Frame_in Loop Filter VCO (~1.3545 GHz) ÷ 4 or 5 (is125M) ÷3 ÷2 Current Source AFS_div TOF4 AFS_mode Figure 8. PLL4 Block Diagram CLOCK OUTPUT JITTER Several of the circuits which require video clocks, such as the embedded Serializers and Deserializers found in FPGAs are sensitive to jitter.
PAGE 27
LMH1983 www.ti.com SNLS309G – APRIL 2010 – REVISED JANUARY 2011 Figure 9. CLKout1 Jitter Histogram Horizontal scale: 2.6ps / division Figure 10. CLKout1 Phase Noise Figure 11. CLKout2 Jitter Histogram Horizontal scale: 4.4ps / division Figure 12. CLKout2 Phase Noise Figure 13. CLKout3 Jitter Histogram Horizontal scale: 4.4ps / div Figure 14.
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LMH1983 SNLS309G – APRIL 2010 – REVISED JANUARY 2011 www.ti.com Figure 15. CLKout4 Jitter Histogram Horizontal scale: 7 ps / div Figure 16. CLKout4 Phase Noise OUTPUT DRIVER ADJUSTMENTS The LVDS output drivers can be adjusted via the I2C interface to change the differential output voltage swing, the common mode voltage and to apply pre-emphasis to the LVDS output Register 0x3A MSB (bit 7) turns on the pre-emphasis which may be used to extend the reach between the LMH1983 and the load.
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LMH1983 www.ti.com SNLS309G – APRIL 2010 – REVISED JANUARY 2011 The alignment between the incoming FIN and the TOF1 output may be controlled in a number of ways. There are three different alignment modes in which TOF1 may operate, selected via register 0x11h. The default, powerup mode is for there to be no alignment, the other two options are to always force alignment to FIN, and to force alignment to FIN when they are misaligned.
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LMH1983 SNLS309G – APRIL 2010 – REVISED JANUARY 2011 www.ti.com Figure 18. TOF1 Timing Top Trace CLKout1, Bottom Trace TOF1 10ns / div. Top 200mV / div, Bottom 1V / div Figure 19. TOF2 Timing Top Trace CLKout2, Bottom Trace TOF2 4ns / div, Top 200mV / div, Bottom 1V / div Figure 20. TOF3 Timing Top Trace CLKout3, Bottom Trace TOF3 4ns / div, Top 200mV / div, Bottom 1V / div Figure 21.
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LMH1983 www.ti.com SNLS309G – APRIL 2010 – REVISED JANUARY 2011 TYPICAL INTERFACE CIRCUIT A typical application circuit for the LMH1983 is shown in the Typical Interface Circuit. The key areas to consider on this circuit are the loop filter – which consists of RS, CS, CP and the LM7711 Operational Amplifier which buffers the loop filter output prior to driving the control voltage input of the VCXO.
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LMH1983 SNLS309G – APRIL 2010 – REVISED JANUARY 2011 www.ti.com TYPICAL APPLICATION BLOCK DIAGRAMS Three typical applications are shown below for the LMH1983 illustrating different input and output options. LOOP FILTER H blank 525i/29.97 digital V blank blanking pulse inputs from FPGA SDI RX F blank 27 MHz VCXO 27 MHz 525i/29.97 SDI out + embedded audio 148.5 MHz (PLL2) 1080i/29.
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LMH1983 www.ti.com SNLS309G – APRIL 2010 – REVISED JANUARY 2011 PCB DESIGN DO's and DON'Ts • • • • • • • • DO whenever possible dedicate an entire layer to each power supply. This will reduce the inductance in the supply plane. DO use surface mount components whenever possible. DO place bypass capacitors and filter components as close as possible to each power pin. DO place the loop filter components, including the buffer amplifier, and VCXO as close as possible to the LMH1983.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LMH1983SQ/NOPB WQFN RTA 40 LMH1983SQE/NOPB WQFN RTA LMH1983SQX/NOPB WQFN RTA SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1 40 250 178.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMH1983SQ/NOPB WQFN RTA 40 1000 367.0 367.0 38.0 LMH1983SQE/NOPB WQFN RTA 40 250 213.0 191.0 55.0 LMH1983SQX/NOPB WQFN RTA 40 2500 367.0 367.0 38.
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MECHANICAL DATA RTA0040A SQA40A (Rev B) www.ti.
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