Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - Op-amp Variable gain WQFN 32 (5x5)

GAIN 0-5

200

ADC

LATCH

½ LMH6517

LMH6517

www.ti.com

SNOSB19K –NOVEMBER 2008–REVISED MARCH 2013

Low Power, Low Noise, IF and Baseband, Dual 16 bit ADC Driver With Digitally Controlled

Gain

Check for Samples: LMH6517

FEATURES

DESCRIPTION

The LMH6517 contains two high performance,

• Accurate, 0.5dB Gain Steps

digitally controlled variable gain amplifiers (DVGA). It

• 200Ω Resistive, Differential Input

has been designed for use in narrowband and

• Low Impedance, Differential Output

broadband IF sampling applications. Typically the

LMH6517 drives a high performance ADC in a broad

• Disable Function for Each Channel

range of mixed signal and digital communication

• Parallel Gain Control

applications such as mobile radio and cellular base

• SPI Compatible Serial Bus

stations where automatic gain control (AGC) is

required to increase system dynamic range.

• Two Wire, Pulse Mode Control

• On Chip Register Stores Gain Setting

Each channel of LMH6517 has an independent,

digitally controlled attenuator and a high linearity,

• Low Sensitivity of Linearity and Phase to Gain

differential output amplifier. Each block has been

Setting

optimized for low distortion and maximum system

• Single 5V Supply Voltage

design flexibility. Each channel can be individually

• Small Footprint WQFN Package

disabled for power savings.

The LMH6517 digitally controlled attenuator provides

APPLICATIONS

precise 0.5dB gain steps over a 31.5dB range. On

• Cellular Base Stations chip digital latches are provided for local storage of

the gain setting. Both serial and parallel programming

• IF Sampling Receivers

options are provided. A Pulse mode is also offered

• Instrumentation

where simple up or down commands can change the

• Modems

gain one step at a time.

• Imaging

The output amplifier has a differential output allowing

large signal swings on a single 5V supply. The low

KEY SPECIFICATIONS

impedance output provides maximum flexibility when

driving filters or analog to digital converters.

• OIP3: 43dBm @ 200MHz

The LMH6517 operates over the industrial

• Noise figure 5.5dB

temperature range of −40°C to +85°C. The LMH6517

• Gain step size of 0.5dB

is available in a 32-Pin, thermally enhanced, WQFN

• Gain step accuracy: 0.05dB

package.

• Frequency Range of 1200 MHz

• Supply current 80mA per channel

Typical Application: IF Sampling Receiver

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (34 pages)

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LMH6517 www.ti.com SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013 Low Power, Low Noise, IF and Baseband, Dual 16 bit ADC Driver With Digitally Controlled Gain Check for Samples: LMH6517 FEATURES DESCRIPTION • • • • • • • • • The LMH6517 contains two high performance, digitally controlled variable gain amplifiers (DVGA). It has been designed for use in narrowband and broadband IF sampling applications.
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LMH6517 SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings ESD Tolerance (1) (2) (3) Human Body Model 2 kV Machine Model 100V Charged Device Model 750V −0.6V to 5.5V Positive Supply Voltage (Pin 3) Differential Voltage between Any Two Grounds <200 mV −0.
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LMH6517 www.ti.com SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013 5V Electrical Characteristics (1) The following specifications apply for single supply with V+ = 5V, Maximum Gain , RL = 100Ω, VOUT = 2 VPP, fin = 150 MHz. Boldface limits apply at temperature extremes. Parameter Test Conditions Min (2) Typ (3) Max (2) Units Dynamic Performance SSBW OIP3 IMD3 P1dB Frequency Range 1200 MHz Maximum Voltage Gain f = 200 MHz 22 dB Input Noise Voltage Maximum Gain, f > 1MHz, RIN= 0 Ω 1.
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LMH6517 SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013 www.ti.com 5V Electrical Characteristics (1) (continued) The following specifications apply for single supply with V+ = 5V, Maximum Gain , RL = 100Ω, VOUT = 2 VPP, fin = 150 MHz. Boldface limits apply at temperature extremes. Parameter Gain Step Phase Shift Test Conditions Min (2) between any two steps Gain Step Switching Time Typ (3) Max (2) Units 0.
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LMH6517 www.ti.com SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013 CONNECTION DIAGRAM A2/CS/S1A A1/SDO/S0A IPA+ IPA- GND +5V GND A0 32 31 30 29 28 27 26 25 Top View A3/SDI/DNA 1 24 OPA+ A4/CLK/UPA 2 23 OPA- 22 ENA LMH6517 A5 3 MOD0 4 21 LATA MOD1 5 20 LATB B5 6 19 ENB B4/UPB 7 18 OPB- 17 OPB+ 9 10 11 12 13 14 15 16 B1/S0B IPB+ IPB- GND +5V GND B0 8 B2/S1B B3/DNB GND Figure 1.
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LMH6517 SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013 www.ti.com PIN DESCRIPTIONS (continued) Pin Number 21, 20 6 Pin Name LATA, LATB Description Latch pins. Logic zero = active, logic 1 = latched. Gain will not change once latch is high. Connect to ground if the latch function is not desired.
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LMH6517 www.ti.com SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013 PIN DESCRIPTIONS (continued) Pin Number Pin Name Description Digital Inputs Serial Mode (MOD1 =1 , MOD0 = 0) 2 CLK Serial Clock 1 SDI Serial Data In (SPI Compatible) See Application Information for more details. 32 CS Serial Chip Select (SPI compatible) 31 SDO Serial Data Out (SPI compatible) 3, 4, 6 — 10, 16, 20, GND 21, 25 Pins unused in Serial Mode, connect to DC ground.
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LMH6517 SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics VCC = 5V Frequency Response 2dB Gain Steps Transformer Coupled Frequency Response 2dB Gain Steps 30 RL = 120Ö & 5 pF 25 20 15 GAIN (dB) GAIN (dB) 20 15 10 10 5 5 0 0 -5 -5 -10 -10 10 100 1000 1 10k 10 FREQUENCY (MHz) Figure 2. -40 °C 0 °C 20 °C 50 °C 80 °C 0.75 GROUP DELAY (ns) 22.4 GAIN (dB) Group Delay 1.00 22.6 22.2 22.0 21.8 21.6 21.4 0 50 100 150 200 250 FREQUENCY (MHz) 0.
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LMH6517 www.ti.
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LMH6517 SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VCC = 5V Cumulative Gain Error vs Attenuator Setting Cumulative Gain Error over Temperature 0.4 f = 200 MHz 0.3 0.3 0.2 GAIN ERROR (dB) CUMULATIVE GAIN ERROR (dB) 0.4 0.2 CH A 0.1 CH B 0.0 0.1 TEMP = -40 0 TEMP = 25 -0.1 -0.2 -0.1 -0.3 TEMP = 85 -0.2 0 6 13 19 26 -0.
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LMH6517 www.ti.
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LMH6517 SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013 www.ti.
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LMH6517 www.ti.com SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VCC = 5V Output Offset Voltage vs. Temperature Pulse Response 4 RL = 200: and 4.7 pF ATT = 0 dB 3 DIFFERENTIAL VOUT (V) 5 ATT = 8 dB 0 ATT = 24 dB -5 2 1 0 -1 -2 -3 ATT = 16 dB ATT = 31 dB -10 -40 -20 0 20 40 60 80 -4 0 100 120 TEMPERATURE (°C) 25 Enable Timing Maximum Gain ENABLE 3.0 0.3 0.2 2.5 0.2 0.1 2.0 1.5 -0.1 1.0 VOUT 0.
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LMH6517 SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VCC = 5V Input Impedance (S11) Output Impedance (S22) 250 50 |Z| 40 OUTPUT IMPEDANCE (:) INPUT IMPEDANCE (:) 200 150 R 100 50 jX |Z| 30 R 20 10 0 0 jX -50 10 100 1000 -10 10 FREQUENCY (MHz) 1000 FREQUENCY (MHz) Figure 38. 14 100 Figure 39.
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LMH6517 www.ti.com SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013 APPLICATION INFORMATION The LMH6517 is a fully differential amplifier optimized for signal path applications up to 400 MHz. The LMH6517 has a 200Ω input and a low impedance output. The gain is digitally controlled over a 31.5 dB range from +22dB to −9.5dB. The LMH6517 is optimized for accurate gain steps and minimal phase shift combined with low distortion products.
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LMH6517 SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013 www.ti.com Channel A 0 to - 31.5 dB Attenuator 22 dB Attenuator 0 to - 31.5 dB 22 dB Channel B Figure 42. LMH6517 Block Diagram INPUT CHARACTERISTICS The LMH6517 input impedance is set by internal resistors to a nominal 200Ω. Process variations will result in a range of values as shown in the 5V Electrical Characteristics table. At higher frequencies parasitic reactances will start to impact the impedance.
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LMH6517 www.ti.com SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013 Excel can also be used for simple circuits; however, the “Analysis ToolPak” add-in must be installed to calculate complex numbers. OUTPUT CHARACTERISTICS The LMH6517 has a low impedance output very similar to a traditional Op-amp output. This means that nearly any load can be driven with minimal gain loss.
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LMH6517 SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013 www.ti.com 10 f = 140 MHz 0.01P + 200: 4.7p LMH6517 220n 10 . - +IN 12p 100 100 12p VRM ADC16DV160 -IN 0.01P Figure 45. Output Configuration DIGITAL CONTROL The LMH6517 will support three modes of control, parallel mode, serial mode (SPI compatible) and pulse mode. Parallel mode is fastest and requires the most board space for logic line routing. Serial mode is compatible with existing SPI compatible systems.
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LMH6517 A2 A1 IPA+ IPA- GND +5V GND A0 31 30 29 28 27 26 25 SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013 32 www.ti.com A3 1 24 OPA+ A4 2 23 OPA- A5 3 22 ENA +3.3/NC 4 21 LATA +3.3/NC 5 20 LATB B5 6 19 ENB B4 7 18 OPB- B3 8 17 OPB+ LMH6517 13 14 GND +5V 16 12 IPB- B0 11 IPB+ 15 10 B1 GND 9 B2 GND Figure 46. Pin Functions for Parallel Mode The LMH6517 has a 6-bit gain control bus as well as a Latch pin.
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LMH6517 SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013 www.ti.com FPGA/DSP/PC/ASIC DVGA VSS 6 ga[5:0] 6 gb[5:0] VSS latcha cmode ga[5:0] gb[5:0] Pins: 13 MSPS: 333 High Skew latchb pd pd VSS Figure 48. Parallel Mode Connection Not Using Latch Pins (Latch pins tied to logic low state) FPGA/DSP/PC/ASIC DVGA latcha ga/gb[5:0] latcha 6 cmode VSS ga[5:0] gb[5:0] latchb pd latchb pd Pins: 9 MSPS: 62.5 Low Skew Figure 49.
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LMH6517 CS SDO IPA+ IPA- GND +5V GND GND 31 30 29 28 27 26 25 SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013 32 www.ti.com SDI 1 24 OPA+ CLK 2 23 OPA- GND 3 22 ENA GND 4 21 GND +3.3/NC 5 20 GND GND 6 19 ENB GND 7 18 OPB- GND 8 17 OPB+ LMH6517 9 10 11 12 13 14 15 16 GND GND IPB+ IPB- GND +5V GND GND GND Figure 50. Pin Functions for Serial Mode The LMH6517 has a serial interface that allows access to the control registers.
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LMH6517 SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013 www.ti.com SDO: This is the data output pin. Ths SDO pin is an open drain output and requires an external bias resistor. See Figure 51 for resistor sizing guidance. This output is normally at TRI-STATE and is driven only when SCSb is asserted. Upon SCSb assertion, contents of the register addressed during the first byte are shifted out with the second 8 SCLK falling edges. Upon power-up, the default register address is 00h.
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LMH6517 www.ti.com SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013 R/Wb Read / Write bit. A value of 1 indicates a read operation, while a value of 0 indicates a write operation. Reserved Not used. Must be set to 0. ADDR: Address of register to be read or written. DATA In a write operation the value of this field will be written to the addressed register when the chip select pin is deasserted. In a read operation this field is ignored.
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LMH6517 SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013 www.ti.com Table 3. Serial Word Format for LMH6517 C7 1= read 0=write C6 0 C5 C4 0 C3 0 C2 0 C1 0 0 C0 0=Ch A 1=Ch B Table 4. Serial Word Format for LMH6517 (cont) Enable 1=On 0=Off Gb5 1=+16dB Gb4 Gb3 1=+8dB Gb2 1=+4dB Gb1 1=+2dB Gb0 1=+1dB 1=+0.5dB RES 0 PULSE MODE (MOD1= 0, MOD0 = 1) S1A S0A IPA+ IPA- GND +5V GND GND 32 31 30 29 28 27 26 25 Pulse mode is a simple yet fast way to adjust gain settings.
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LMH6517 www.ti.com SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013 PULSE TIMING tPW tPG UP/DN RESET TIMING UP tRW DN Figure 56. Pulse Mode Timing EXPOSED PAD WQFN PACKAGE The LMH6517 is packaged in a thermally enhanced package. The exposed pad is connected to the GND pins. It is recommended, but not necessary, that the exposed pad be connected to the supply ground plane. In any case, the thermal dissipation of the device is largely dependent on the attachment of this pad.
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LMH6517 SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013 www.ti.com ADC Noise Filter Below are filter schematics and a table of values for some common IF frequencies. The filter shown in Figure 58 offers a good compromise between bandwidth, noise rejection and cost. This filter topology is the same as is used on the ADC14V155KDRB High IF Receiver reference design board. This filter topology works best with the 12 and 14 bit sub-sampling analog to digital converters shown in the Table 6 table. Table 5.
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LMH6517 www.ti.com SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013 AMP VOUT - 5 91n 240n 18n ADC VIN + 4.7p ADC ZIN 100 27p 5.2p 100 ADC VIN 5 AMP VOUT + 91n 240n ADC VCM Figure 59. Impedance Transforming Filter 25 Ω Input 200 Ω Output, 210 MHz Center Frequency POWER SUPPLIES The LMH6517 was designed primarily to be operated on 5V power supplies. The voltage range for VCC is 4.5V to 5.25V. A 5V supply provides the best performance while lower supplies will result in less power consumption.
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LMH6517 SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013 www.ti.com Table 6.
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LMH6517 www.ti.com SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision J (March 2013) to Revision K • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LMH6517SQ/NOPB WQFN RTV 32 LMH6517SQE/NOPB WQFN RTV LMH6517SQX/NOPB WQFN RTV SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 32 250 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 32 4500 330.0 12.4 5.3 5.3 1.3 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMH6517SQ/NOPB WQFN RTV 32 1000 213.0 191.0 55.0 LMH6517SQE/NOPB WQFN RTV 32 250 213.0 191.0 55.0 LMH6517SQX/NOPB WQFN RTV 32 4500 367.0 367.0 35.
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MECHANICAL DATA RTV0032A SQA32A (Rev B) www.ti.
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