Datasheet

Equivalent Output Circuitry
Current 3.25 mA
+
-
Current 3.25 mA
CM loop
V
REF
+
-
Output Q
Output Q
VCC
LMH7220
SNOSAL3E –SEPTEMBER 2006–REVISED MAY 2013 www.ti.com
The output can be seen as a bridge configuration in which switches are crosswise closed, producing the
differential LVDS logic high and low levels (see Figure 20). The output switches are fed at top and bottom by two
current sources. The top one is fixed and determines the differential voltage across the external load resistor.
The other one is regulated and determines the common-mode voltage on the outputs. It is essential to keep the
output common-mode voltage at the defined standardized LVDS level under all circumstances. To realize this,
both outputs are internally connected together via two equal resistors. At the midpoint this produces the common
mode output voltage, which is made equal to V
REF
(1.2V) by means of the CM feedback loop.
Figure 20. Equivalent Output Circuitry
DEFINITIONS
For a good understanding of many parameters of the LMH7220 it is necessary to perform a lot of measurements.
All of those parameters are listed in the data tables in the first part of the datasheet. There are different tables for
several supply voltages containing a separate set of data per supply voltage. In the table below is a list of
abbreviations of the measured parameters and a short description of the conditions which are applied for
measuring them . Following this table several parameters are highlighted to explain more clearly what it means
exactly and what effects such a phenomena can have for any applied electronic circuit.
Symbol Text Description
I
B
Input Bias Current Current flowing in or out the input pins, when both biased at 0.3 Volt above
GND
I
OS
Input Offset Current Difference between the positive- and the negative input currents needed to
make the outputs change state, averaged for H to L and L to H transitions
TC I
OS
Average Input Offset Current Drift Temperature Coefficient of I
OS
V
OS
Input Offset Voltage Voltage difference needed between IN
+
and IN
−
to make the outputs
change state, averaged for H to L and L to H transitions
TC V
OS
Average Input Offset Voltage Drift Temperature Coefficient of V
OS
CMRR Common Mode Rejection Ratio Ratio of input offset voltage change and input common mode voltage
change
VRI Input Voltage Range Upper and lower limits of the input voltage are defined as where CMRR
drops below 50 dB.
PSRR Power Supply Rejection Ratio Ratio of input offset voltage change and supply voltage change from V
S-MIN
to V
S-MAX
V
O
Output Offset Voltage Output Common Mode Voltage averaged for logic ‘0’ and logic ‘1’ levels
(See Figure 30)
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