Datasheet

Hysteresis
Input Signal
Output
t = 0
t = 1
0
1
mV
Vref
A
B
LMH7220
www.ti.com SNOSAL3E –SEPTEMBER 2006–REVISED MAY 2013
The divider R
F
-R
P
feeds back a portion of the output voltage to the positive input. Only a small part of the output
voltage is needed, just enough to avoid the area at which the input is in an undefined state. Assuming this is only
a few millivolts, it is sufficient to add (plus or minus) 10 mV to the positive input to prevent the circuit from
oscillations. If the output switches between 0V and 5V and the choice for one of the resistors is done the other
can be calculated. Assume R
P
is 50Ω then R
F
is 25 kΩ for 10 mV threshold on the positive input. The situation of
Figure 29 is now created.
Figure 29. Hysteresis
In this picture there are two dotted lines, A and B, both indicating the resulting level at the positive input. When
the signal at the negative input is low, the state of the input stage is well defined with the negative input much
lower than the positive input. As a result the output will be in the high state. The positive input is at level A. With
the input signal sloping up, this situation remains until V
IN
crosses level A at t=1. Now the output toggles, and the
voltage at the positive input is lowered to level B. So before the output has the possibility to toggle again, the
difference between both inputs is made sufficient to have a stable situation again. When the input signal comes
down from high to low, the situation is stable until level B is reached at t=0. At this moment the output will toggle
back, and the circuit is back in the start situation with the negative input at a much lower level than the positive
one. In the situation without hysteresis, the output would toggle exactly at V
REF
. With hysteresis this happens at
the introduced levels A and B, as can be seen in Figure 29. Varying the levels A and B will also vary the timing of
t=0 and t=1. When designing a circuit be aware of this effect. Introducing hysteresis will cause some time shifts
between output and input (e.g. duty cycle variations), but eliminates undesired switching of the output.
Parasitic Capacitors
In the simple schematic of Figure 28 some capacitors are drawn. The capacitors C
P
. represent the parasitic
(board) capacitance at the input of the part. This capacity will slow down the change of the level of the positive
input in reaction to the changing output voltage. As a result of this, the output may have the time to switch over
more than once. Actually the parasitic capacity represented by C
P
makes the attenuation circuit of R
F
and R
P
frequency dependent. The only action to take is to create a frequency independent circuit. This is simply done by
placing the compensation capacitor C
C
in parallel with R
F
. The capacitor C
C
can be calculated with the formula
R
F
*C
C
= R
P
*C
P
; this means that both of the time constants must be the same to create a frequency
independent network. A simple example gives the following assuming that C
P
is in total 2.5 pF and as already
calculated R
F
= 25 kΩ in combination with R
P
= 50Ω. These input data gives:
C
C
= R
P
* C
P
/R
F
(1)
C
C
= 50*2.5e-12/25e3 (2)
C
C
= 5e-15 = 0.005 pF (3)
This is not a practical value and different conclusions are possible:
• No capacitor C
C
needed
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