Datasheet

V
ODH
V
ODL
'0' '1'
'V
O
'0'
Output Q
Output Q
'V
OD
= | V
ODH
- V
ODL
|
V
OD
= (V
ODH
+ V
ODL
) / 2
V
OH
V
O
V
OL
V
OD
Output Q
Output Q
LMH7220
SNOSAL3E –SEPTEMBER 2006–REVISED MAY 2013 www.ti.com
• Place a capacitor C
C
of 1 pF and accept a big overshoot at the positive input being sure that the input stage
is in a secure new position
• Place an extra C
P
of such a value that C
C
has a realistic value of say 1 pF (extra C
P
= ±500 pF).
Position of Feedback Resistors
Another important issue while using positive feedback is the placement of the resistors R
P
and R
F
. These
resistors must be placed as near as possible to the positive input, because this input is most sensitive for picking
up spurious signals, noise etc. This connection must be very clean for the best performance of the overall circuit.
With raising speeds the total PCB design becomes more and more critical, the LMH7220 comparator doesn’t
have built in hysteresis, so the input signal must meet minimum requirements to make the output switch over
properly. In the following sections some aspects concerning the load connected to the outputs and transmission
lines will be discussed.
THE OUTPUT SWING PROPERTIES
LVDS has differential outputs which means that both outputs have the same swing but in opposite direction
(Figure 30). Both outputs swing around a voltage called the common mode output voltage (V
O
). This voltage can
be measured at the midpoint of two equal resistors connected to both outputs as discussed in INPUT & OUTPUT
TOPOLOGY. The absolute value of the difference between both voltages is called V
OD
. LVDS outputs cannot be
held at the V
O
level because of their digital nature. They only cross this level during a transition. Due to the
symmetrical structure of the circuit, both output voltages cross at V
O
regardless if the output changes from ‘0’ to
‘1’ or vise versa.
Figure 30. LVDS Output Signals
In case the outputs aren’t symmetrical or are a-symmetrically loaded, the output voltages differ from the situation
of Figure 30. For this non-ideal situation there are two additional parameters defined, ΔV
O
and ΔV
OD
, as can be
seen in Figure 31.
Figure 31. LVDS Output Signals with Different Amplitude
ΔV
O
is the difference in V
O
between the ‘1’ state and the ‘0’ state. This variation is acceptable if it is below 50 mV
following the ANSI/TIA/EIA-644 LVDS standard. It is also possible that V
OD
in the ‘1’ state isn’t the same as in
the ‘0’ state. This parameter is specified as ΔV
OD
, and is calculated as the absolute value of the difference of
V
ODH
and V
ODL
.
22 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LMH7220