Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - Op-amp Multi-purpose SOT 23 5

LMP7701, LMP7702, LMP7704

www.ti.com

SNOSAI9H –SEPTEMBER 2005–REVISED MARCH 2013

LMP7701/LMP7702/LMP7704 Precision, CMOS Input, RRIO, Wide Supply Range Amplifiers

Check for Samples: LMP7701, LMP7702, LMP7704

FEATURES

DESCRIPTION

The LMP7701/LMP7702/LMP7704 are single, dual,

• Unless Otherwise Noted,

and quad low offset voltage, rail-to-rail input and

Typical Values at V

= 5V

output precision amplifiers each with a CMOS input

– Input Offset Voltage (LMP7701): ±200 µV

stage and a wide supply voltage range. The

(max)

LMP7701/LMP7702/LMP7704 are part of the LMP™

precision amplifier family and are ideal for sensor

– Input Offset Voltage (LMP7702/LMP7704):

interface and other instrumentation applications.

±220 µV (max)

– Input Bias Current: ±200 fA

The specified low offset voltage of less than ±200 µV

along with the specified low input bias current of less

– Input Bias Current: ±200 fA

than ±1 pA make the LMP7701 ideal for precision

– Input Voltage Noise: 9 nV/√Hz

applications. The LMP7701/LMP7702/LMP7704 are

– CMRR: 130 dB

built utilizing VIP50 technology, which allows the

combination of a CMOS input stage and a 12V

– Open Loop Gain: 130 dB

common mode and supply voltage range. This makes

– Temperature Range: −40°C to 125°C

the LMP7701/LMP7702/LMP7704 great choices in

– Unity Gain Bandwidth: 2.5 MHz

many applications where conventional CMOS parts

cannot operate under the desired voltage conditions.

– Supply Current (LMP7701): 715 µA

– Supply Current (LMP7702): 1.5 mA

The LMP7701/LMP7702/LMP7704 each have a rail-

to-rail input stage that significantly reduces the CMRR

– Supply Current (LMP7704): 2.9 mA

glitch commonly associated with rail-to-rail input

– Supply Voltage Range: 2.7V to 12V

amplifiers. This is achieved by trimming both sides of

– Rail-to-Rail Input and Output

the complimentary input stage, thereby reducing the

difference between the NMOS and PMOS offsets.

APPLICATIONS

The output of the LMP7701/LMP7702/LMP7704

swings within 40 mV of either rail to maximize the

• High Impedance Sensor Interface

signal dynamic range in applications requiring low

• Battery Powered Instrumentation

supply voltage.

• High Gain Amplifiers

The LMP7701 is offered in the space saving 5-Pin

• DAC Buffer

SOT-23 and 8-Pin SOIC package. The LMP7702 is

offered in the 8-Pin SOIC and 8-Pin VSSOP package.

• Instrumentation Amplifier

The quad LMP7704 is offered in the 14-Pin SOIC and

• Active Filters

14-Pin TSSOP package. These small packages are

ideal solutions for area constrained PC boards and

portable electronics.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2LMP is a trademark of Texas Instruments.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (35 pages)

PAGE 1
LMP7701, LMP7702, LMP7704 www.ti.com SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 LMP7701/LMP7702/LMP7704 Precision, CMOS Input, RRIO, Wide Supply Range Amplifiers Check for Samples: LMP7701, LMP7702, LMP7704 FEATURES DESCRIPTION • The LMP7701/LMP7702/LMP7704 are single, dual, and quad low offset voltage, rail-to-rail input and output precision amplifiers each with a CMOS input stage and a wide supply voltage range.
PAGE 2
LMP7701, LMP7702, LMP7704 SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com TYPICAL APPLICATION R R V1 V + - RS I = (V2 ± V1) A1 RS + V - V + Z R LOAD - R V2 A2 + - V Figure 1. Precision Current Source Absolute Maximum Ratings ESD Tolerance (3) (1) (2) Human Body Model 2000V Machine Model 200V Charge-Device Model 1000V VIN Differential ±300 mV Supply Voltage (VS = V+ – V−) 13.2V V++ 0.3V, V− − 0.
PAGE 3
LMP7701, LMP7702, LMP7704 www.ti.com SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 Operating Ratings Temperature Range (1) (2) −40°C to +125°C Supply Voltage (VS = V+ – V−) 2.7V to 12V Package Thermal Resistance (θJA (2)) (1) (2) 5-Pin SOT-23 265°C/W 8-Pin SOIC 190°C/W 8-Pin VSSOP 235°C/W 14-Pin SOIC 145°C/W 14-Pin TSSOP 122°C/W Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
PAGE 4
LMP7701, LMP7702, LMP7704 SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com 3V Electrical Characteristics (1) (continued) Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 3V, V− = 0V, VCM = V+/2, and RL > 10 kΩ to V+/2. Boldface limits apply at the temperature extremes.
PAGE 5
LMP7701, LMP7702, LMP7704 www.ti.com SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 5V Electrical Characteristics (1) Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5V, V− = 0V, VCM = V+/2, and RL > 10 kΩ to V+/2. Boldface limits apply at the temperature extremes. Parameter VOS Test Conditions Input Offset Voltage TCVOS IB Input Offset Voltage Temperature Drift Min (2) (3) ±200 ±500 LMP7702/LMP7704 ±32 ±220 ±520 ±1 ±5 ±0.2 ±1 ±50 ±0.
PAGE 6
LMP7701, LMP7702, LMP7704 SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com 5V Electrical Characteristics (1) (continued) Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5V, V− = 0V, VCM = V+/2, and RL > 10 kΩ to V+/2. Boldface limits apply at the temperature extremes.
PAGE 7
LMP7701, LMP7702, LMP7704 www.ti.com SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 ±5V Electrical Characteristics (1) (continued) Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5V, V− = −5V, VCM = 0V, and RL > 10 kΩ to 0V. Boldface limits apply at the temperature extremes. Parameter Test Conditions + Min (2) Typ (3) PSRR Power Supply Rejection Ratio 2.7V ≤ V ≤ 12V, VO = 0V CMVR Common Mode Voltage Range CMRR ≥ 80 dB CMRR ≥ 78 dB −5.2 −5.
PAGE 8
LMP7701, LMP7702, LMP7704 SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com CONNECTION DIAGRAMS OUT - V 5 1 N/C -IN 2 + IN+ + V - 3 +IN 4 IN- 1 2 3 8 + 4 6 5 V 8 7 N/C + V OUTPUT N/C Figure 2. 5-Pin SOT-23 (LMP7701) Top View Figure 3. 8-Pin SOIC (LMP7701) Top View Figure 4. 8-Pin SOIC/VSSOP (LMP7702) Top View Figure 5.
PAGE 9
LMP7701, LMP7702, LMP7704 www.ti.com SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 Typical Performance Characteristics Unless otherwise noted: TA = 25°C, VCM = VS/2, RL > 10 kΩ. Offset Voltage Distribution TCVOS Distribution 20 25 VS = 3V VS = 3V -40°C d TA d 125°C 16 PERCENTAGE (%) PERCENTAGE (%) 20 TA = 25°C 15 10 12 8 4 5 0 -200 0 -100 0 100 200 -3 -2 -1 0 TCVOS (PV/°C) Figure 6. Figure 7.
PAGE 10
LMP7701, LMP7702, LMP7704 SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise noted: TA = 25°C, VCM = VS/2, RL > 10 kΩ. CMRR vs. Frequency 200 0 150 -20 VS = 3V 100 -40 VS = 3V 50 VS = 5V CMRR (dB) OFFSET VOLTAGE (PV) Offset Voltage vs. Temperature 0 -50 VS = 5V VS = 10V -80 -100 -100 VS = 10V -120 -150 -200 -140 -40 -20 0 20 40 60 80 100 120125 10 Figure 12. Figure 13. Offset Voltage vs.
PAGE 11
LMP7701, LMP7702, LMP7704 www.ti.com SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise noted: TA = 25°C, VCM = VS/2, RL > 10 kΩ. Input Bias Current vs. VCM Input Bias Current vs. VCM 300 200 VS = 3V VS = 3V 200 100 IBIAS (pA) IBIAS (fA) 100 -40°C 0 85°C 0 -100 -100 -200 125°C 25°C -300 -200 0 0.5 1 2 1.5 2.5 0 3 0.5 1.5 1 Figure 18. Figure 19. Input Bias Current vs. VCM Input Bias Current vs.
PAGE 12
LMP7701, LMP7702, LMP7704 SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise noted: TA = 25°C, VCM = VS/2, RL > 10 kΩ. PSRR vs. Frequency 120 Supply Current vs. Supply Voltage (Per Channel) 1.2 VS = 10V VS = 5V 1 SUPPLY CURRENT (mA) 100 VS = 3V +PSRR PSRR (dB) 80 VS = 10V 60 VS = 5V VS = 3V 40 20 125°C 25°C 0.8 0.6 -40°C 0.4 0.
PAGE 13
LMP7701, LMP7702, LMP7704 www.ti.com SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise noted: TA = 25°C, VCM = VS/2, RL > 10 kΩ.
PAGE 14
LMP7701, LMP7702, LMP7704 SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise noted: TA = 25°C, VCM = VS/2, RL > 10 kΩ. Input Voltage Noise vs. Frequency Open Loop Gain vs. Output Voltage Swing 150 VS = 10V 100 80 VS = 3V 60 VS = 5V 40 130 120 RL = 10 k: 110 VS = 3V 100 90 80 20 1 10 RL = 2 k: 70 VS = 10V 0 100 1k 10k 60 500 100k FREQUENCY (Hz) 400 100 0 Output Swing High vs. Supply Voltage Output Swing Low vs.
PAGE 15
LMP7701, LMP7702, LMP7704 www.ti.com SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise noted: TA = 25°C, VCM = VS/2, RL > 10 kΩ. THD+N vs. Frequency THD+N vs. Output Voltage 1 1 VS = 5V f = 1 kHz VS = 5V VO = 4.5 VPP RL = 100 k: RL = 100 k: 0.1 THD+N (%) 0.1 AV = +10 THD+N (%) AV = +10 0.01 0.01 AV = +1 AV = +1 0.001 10 100 1k 10k 0.001 0.001 100k 0.01 0.1 FREQUENCY (Hz) VOUT (V) Figure 42. Figure 43.
PAGE 16
LMP7701, LMP7702, LMP7704 SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com APPLICATION INFORMATION LMP7701/LMP7702/LMP7704 The LMP7701/LMP7702/LMP7704 are single, dual, and quad low offset voltage, rail-to-rail input and output precision amplifiers each with a CMOS input stage and wide supply voltage range of 2.7V to 12V. The LMP7701/LMP7702/LMP7704 have a very low input bias current of only ±200 fA at room temperature. The wide supply voltage range of 2.
PAGE 17
LMP7701, LMP7702, LMP7704 www.ti.com SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 amplifier, to form a pole. This pole will have little or no effect on the output of the amplifier at low frequencies and DC conditions, but will play a bigger role as the frequency increases. At higher frequencies, the presence of this pole will decrease phase margin and will also cause gain peaking. In order to compensate for the input capacitance, care must be taken in choosing the feedback resistors.
PAGE 18
LMP7701, LMP7702, LMP7704 SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com Equation 1 has two poles. In most cases, it is the presence of pairs of poles that causes gain peaking. In order to eliminate this effect, the poles should be placed in Butterworth position, since poles in Butterworth position do not cause gain peaking. To achieve a Butterworth pair, the quantity under the square root in Equation 1 should be set to equal −1.
PAGE 19
LMP7701, LMP7702, LMP7704 www.ti.com SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 PRECISION CURRENT SOURCE The LMP7701/LMP7702/LMP7704 can each be used as a precision current source in many different applications. Figure 50 shows a typical precision current source. This circuit implements a precision voltage controlled current source. Amplifier A1 is a differential amplifier that uses the voltage drop across RS as the feedback signal.
PAGE 20
LMP7701, LMP7702, LMP7704 SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com + V + - VIN VOUT - RG RO V RF + V + RG V - RO RF + V + RG V - RO RF + V + RG V - RO RF Figure 51. Noise Reduction Circuit TOTAL NOISE CONTRIBUTION The LMP7701/LMP7702/LMP7704 have very low input bias current, very low input current noise, and very low input voltage noise. As a result, these amplifiers are ideal choices for circuits with high impedance sensor applications.
PAGE 21
LMP7701, LMP7702, LMP7704 www.ti.com SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 VOLTAGE NOISE DENSITY (nV/ Hz) 1000 100 eni en 10 et ei 1 0.1 10 100 1k 10k 100k 1M 10M RS (:) Figure 52. Total Input Noise HIGH IMPEDANCE SENSOR INTERFACE Many sensors have high source impedances that may range up to 10 MΩ. The output signal of sensors often needs to be amplified or otherwise conditioned by means of an amplifier.
PAGE 22
LMP7701, LMP7702, LMP7704 SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com ACID +414 mV BASE 4 7 10 +177 mV 0 mV -177 mV 2 0 14 pH 12 -414 mV Figure 54. Output Voltage of a pH Electrode The temperature dependence of a typical pH electrode is shown in Figure 55. As is evident, the output voltage changes with changes in temperature. mV 600 10°C (74.04 mV/pH) 500 400 25°C (59.15 mV/pH) 300 200 100 2 4 12 10 8 14 pH 0 -100 1 3 5 7 9 11 13 -200 -300 -400 -500 0°C (54.
PAGE 23
LMP7701, LMP7702, LMP7704 www.ti.com SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 + V pH ELECTRODE TEMPERATURE 0.01 PF 0.01 PF 0.1 PF 0.1 PF 10 PF 10 PF + 75: V 1 PF + 1 A1 R2 10 k: R1 10 k: - V+ + V VD + V R3 10 k: R4 10 k: VA + CH0 - VOUT A2 CH1 + RT + V VOFFSET = 0.5012V LM35 -V+ 2 3 LM4140A 6 R5 10 k: - ADC12034 V R6 3.3 k: 1,4,7,8 AGND VREFVREF+ DGND pH ELECTRODE Figure 56.
PAGE 24
LMP7701, LMP7702, LMP7704 SNOSAI9H – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision G (March 2013) to Revision H • 24 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
PAGE 25
PACKAGE OPTION ADDENDUM www.ti.
PAGE 26
PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
PAGE 27
PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMP7701MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMP7701MF SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMP7701MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.
PAGE 28
PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMP7701MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMP7701MF SOT-23 DBV 5 1000 210.0 185.0 35.0 LMP7701MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMP7701MFX SOT-23 DBV 5 3000 210.0 185.0 35.0 LMP7701MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LMP7702MAX/NOPB SOIC D 8 2500 367.0 367.0 35.
PAGE 29
PAGE 30
PAGE 31
PAGE 32
PAGE 33
PAGE 34
PAGE 35
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.