Datasheet

LMP91002

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SNIS163A –APRIL 2012–REVISED MARCH 2013

Control amplifier

The control amplifier (A1 op amp in Figure 17) provides initial charge to the sensor. A1 has the capability to drive

up to 10mA into the sensor in order to to provide a fast initial conditioning. A1 is able to sink and source current

according to the connected gas sensor (reducing or oxidizing gas sensor). It can be powered down to reduce

system power consumption. However powering down A1 is not recommended, as it may take a long time for the

sensor to recover from this situation.

Internal zero

The internal Zero is the voltage at the non-inverting pin of the TIA. The internal zero can be programmed to be

either 67%, 50% or 20%, of the supply, or the external reference voltage. This provides both sufficient headroom

for the counter electrode of the sensor to swing, in case of sudden changes in the gas concentration, and best

use of the ADC’s full scale input range.

The Internal zero is provided through an internal voltage divider (Vref divider box in Figure 17). The divider is

programmed through the I

C interface.

C INTERFACE

The I

C compatible interface operates in Standard mode (100kHz). Pull-up resistors or current sources are

required on the SCL and SDA pins to pull them high when they are not being driven low. A logic zero is

transmitted by driving the output low. A logic high is transmitted by releasing the output and allowing it to be

pulled-up externally. The appropriate pull-up resistor values will depend upon the total bus capacitance and

operating speed. The LMP91002 comes with a 7 bit bus fixed address: 1001 000.

WRITE AND READ OPERATION

In order to start any read or write operation with the LMP91002, MENB needs to be set low during the whole

communication. Then the master generates a start condition by driving SDA from high to low while SCL is high.

The start condition is always followed by a 7-bit slave address and a Read/Write bit. After these 8 bits have been

transmitted by the master, SDA is released by the master and the LMP91002 either ACKs or NACKs the

address. If the slave address matches, the LMP91002 ACKs the master. If the address doesn't match, the

LMP91002 NACKs the master. For a write operation, the master follows the ACK by sending the 8-bit register

address pointer. Then the LMP91002 ACKs the transfer by driving SDA low. Next, the master sends the 8-bit

data to the LMP91002. Then the LMP91002 ACKs the transfer by driving SDA low. At this point the master

should generate a stop condition and optionally set the MENB at logic high level (refer to Figure 20).

A read operation requires the LMP91002 address pointer to be set first, also in this case the master needs

setting at low logic level the MENB, then the master needs to write to the device and set the address pointer

before reading from the desired register. This type of read requires a start, the slave address, a write bit, the

address pointer, a Repeated Start (if appropriate), the slave address, and a read bit (refer to Figure 20).

Following this sequence, the LMP91002 sends out the 8-bit data of the register.

When just one LMP91002 is present on the I

C bus the MENB can be tied to ground (low logic level).

Product Folder Links: LMP91002