Datasheet
D7 D6 D5 D4 D3 D2 D1 D0
1 9
Ack
by
LMP91000
Start by
Master
No Ack
by
Master
SCL
SDA
Stop
by
Master
1 9
Frame 1
Serial Bus Address Byte
from Master
Frame 2
Data Byte from
Slave
R/W
A2
A0A1
A3A4A5A6
MENB
D7 D6 D5 D4 D3 D2 D1 D0
1 9
1 9
Ack
by
LMP91000
Start by
Master
R/W
Ack
by
LMP91000
Frame 1
Serial Bus Address Byte
from Master
Frame 2
Internal Address Register
Byte from Master
A2
A0A1
A3A4A5A6
SCL
SDA
Stop by
Master
MENB
D7 D6 D5 D4 D3 D2 D1 D0
1 9 1 9
Ack
by
LMP91000
Start by
Master
R/W
Ack
by
LMP91000
Frame 1
Serial Bus Address Byte
from Master
Frame 2
Internal Address Register
Byte from Master
1 9
Ack
by
LMP91000
Frame 3
Data Byte
D3
D1D2
D4D5D6D7
A2 A0A1A3A4A5A6
SCL
SDA
SCL
(continued)
SDA
(continued)
Stop by
Master
D0
MENB
MENB
(continued)
LMP91002
SNIS163A –APRIL 2012–REVISED MARCH 2013
www.ti.com
Figure 18. (a) Register write transaction
Figure 19. (b) Pointer set transaction
(c) Register read transaction
Figure 20. READ and WRITE transaction
TIMEOUT FEATURE
The timeout is a safety feature to avoid bus lockup situation. If SCL is stuck low for a time exceeding t_timeout,
the LMP91002 will automatically reset its I
2
C interface. Also, in the case the LMP91002 hangs the SDA for a time
exceeding t_timeout, the LMP91002’s I
2
C interface will be reset so that the SDA line will be released. Since the
SDA is an open-drain with an external resistor pull-up, this also avoids high power consumption when LMP91002
is driving the bus and the SCL is stopped.
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Product Folder Links: LMP91002