Datasheet

LMP91002
www.ti.com SNIS163A –APRIL 2012–REVISED MARCH 2013
REGISTERS
The registers are used to configure the LMP91002.
If writing to a reserved bit, user must write only 0. Readback value is unspecified and should be discarded.
Table 1. Register Map
Address Name Power on default Access Lockable?
0x00 STATUS 0x00 Read only N
0x01 LOCK 0x01 R/W N
0x02 through 0x09 RESERVED
0x10 TIACN 0x03 R/W Y
0x11 REFCN 0x20 R/W Y
0x12 MODECN 0x00 R/W N
0x13 through 0xFF RESERVED
STATUS -- Status Register (address 0x00)
The status bit is an indication of the LMP91002's power-on status. If its readback is “0”, the LMP91002 is not
ready to accept other I
2
C commands.
Bit Name Function
[7:1] RESERVED
Status of Device
0 STATUS 0 Not Ready (default)
1 Ready
LOCK -- Protection Register (address 0x01)
The lock bit enables and disables the writing of the TIACN and the REFCN registers. In order to change the
content of the TIACN and the REFCN registers the lock bit needs to be set to “0”.
Bit Name Function
[7:1] RESERVED
Write protection
0 LOCK 0 Registers 0x10, 0x11 in write mode
1 Registers 0x10, 0x11 in read only mode (default)
TIACN -- TIA Control Register (address 0x10)
The parameters in the TIA control register allow the configuration of the transimpedance gain (R
TIA
).
Bit Name Function
[7:5] RESERVED RESERVED
TIA feedback resistance selection
000 External resistance (default)
001 2.75kΩ
010 3.5kΩ
[4:2] TIA_GAIN 011 7kΩ
100 14kΩ
101 35kΩ
110 120kΩ
111 350kΩ
[1:0] RESERVED RESERVED
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