Datasheet
SCL
SDA
t
HD;STA
t
LOW
t
HD;DAT
t
HIGH
t
SU;DAT
t
SU;STA
t
SU;STO
t
f
START
REPEATED
START
STOP
t
HD;STA
START
t
SP
t
BUF
1/f
SCL
t
VD;DAT
t
VD;ACK
30%
70%
30%
70%
MENB
30%
70%
t
EN;START
t
EN;STOP
t
EN;HIGH
LMP91002
SNIS163A –APRIL 2012–REVISED MARCH 2013
www.ti.com
Timing Characteristics
(1)
Unless otherwise specified, all limits ensured for T
A
= 25°C, V
S
= (VDD – AGND), V
S
= 3.3V and AGND = DGND = 0V, VREF
= 2.5V, Internal Zero= 20% VREF. Boldface limits apply at the temperature extremes. Refer to timing diagram in Figure 3.
Symbol Parameter Conditions Min Typ Max Units
f
SCL
Clock Frequency 10 100 kHz
t
LOW
Clock Low Time 4.7 µs
t
HIGH
Clock High Time 4.0 µs
After this period, the first clock
t
HD;STA
Data valid 4.0 µs
pulse is generated
t
SU;STA
Set-up time for a repeated START condition 4.7 µs
t
HD;DAT
Data hold time
(2)
0 ns
t
SU;DAT
Data Setup time 250 ns
t
f
SDA fall time
(3)
IL ≤ 3mA, CL ≤ 400pF 250 ns
t
SU;STO
Set-up time for STOP condition 4.0 µs
Bus free time between a STOP and START
t
BUF
4.7 µs
condition
t
VD;DAT
Data valid time 3.45 µs
t
VD;ACK
Data valid acknowledge time 3.45 µs
t
SP
Pulse width of spikes that must be
50 ns
suppressed by the input filter
(3)
t_timeout SCL and SDA Timeout 25 100 ms
t
EN;START
I
2
C Interface Enabling 600 ns
t
EN;STOP
I
2
C Interface Disabling 600 ns
t
EN;HIGH
time between consecutive I
2
C interface
600 ns
enabling and disabling
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that T
J
= T
A
. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where T
J
> T
A
. Absolute Maximum Ratings indicate junction temperature limits beyond
which the device may be permanently degraded, either mechanically or electrically.
(2) LMP91002 provides an internal 300ns minimum hold time to bridge the undefined region of the falling edge of SCL.
(3) This parameter is specified by design or characterization.
Timing Diagram
Figure 3. I
2
C Interface Timing Diagram
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