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LMP92001

www.ti.com

SNAS507B –FEBRUARY 2011–REVISED APRIL 2012

LMP92001 Analog System Monitor and Controller

Check for Samples: LMP92001

FEATURES

APPLICATIONS

• 16 Analog Voltage Monitoring Channels

• RF PA Bias Monitoring and Control

– 12-bit ADC with Programmable Input MUX • System Monitoring and Control

– No Missing Codes • Industrial Monitoring and Control

– Total Unadjusted Error (TUE) ±0.1% • Test Equipment and Instrumentation

– Single-Shot or Continuous Conversion

DESCRIPTION

Modes

The LMP92001 is a complete analog monitoring and

– Programmable Window Comparator

control circuit which includes a sixteen channel 12-bit

Function

Analog to Digital Converter (ADC), twelve 12-bit

– Interrupt Signal Generation for Input Out-of-

Digital to Analog Converters (DACs), an internal

Bound Condition

reference, an internal temp sensor, an 8-bit GPIO

port, and an I

C-compatible interface.

• 12 Programmable Analog Voltage Outputs

– Twelve 12-bit DACs

The ADC can be used to monitor rail voltages,

current sense amplifier outputs or sensors and

– Specified Monotonic

includes a programmable window comparator

– Settling Time 8.5 µs

function on six of its 16 channels to detect out-of

– Simultaneous Update of All Channels to

range conditions.

Same Value

The DACs can be used to control PA bias points,

– Asynchronous Output Control Forces Rail

actuators, potentiometers, etc. When required, the

Voltage at Output

outputs can be instantaneously driven to either supply

rail using the output switches and the asynchronous

• Voltage Reference

DAC control inputs.

– User-Selectable Source: External or Internal

Both ADC and DACs can use either the internal 4.5V

– Internal Reference 4.5V ±0.7%

reference or an external reference independently.

• Analog Temperature Sensor

The built-in temperature sensor is treated as the 17th

– Readable via ADC Channel 17

analog sense input. In addition, the 8-bit GPIO port

– Temperature Error ±2°C

allows for the resources of the microcontroller to be

• 8-bit GPIO Port

further extended, providing even more flexibility.

– Each Bit Individually Programmable

The LMP92001 is available in a space saving 54-pin

• I

C-Compatible Bus

WQFN package and is operational over the full −

40°C to 125°C temperature range.

– Supports Standard and Fast Modes

– Bus TIMEOUT Function

– Supports Block Data Transfers

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (39 pages)

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LMP92001 www.ti.com SNAS507B – FEBRUARY 2011 – REVISED APRIL 2012 LMP92001 Analog System Monitor and Controller Check for Samples: LMP92001 FEATURES APPLICATIONS • • • • • 1 2 • • • • • 16 – – – – Analog Voltage Monitoring Channels 12-bit ADC with Programmable Input MUX No Missing Codes Total Unadjusted Error (TUE) ±0.
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LMP92001 SNAS507B – FEBRUARY 2011 – REVISED APRIL 2012 www.ti.com Block Diagram OUT12 IN[16:1] OUT1 16 Temp.
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LMP92001 www.ti.
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LMP92001 SNAS507B – FEBRUARY 2011 – REVISED APRIL 2012 www.ti.com The analog control functionality is served by twelve 12-bit voltage output DACs. Besides producing voltage corresponding to the digital input code, the DACs can be forced by the user to either rail instantaneously. Additional digital monitoring and control can be realized via the General Purpose I/O port GPIO[7:0].
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LMP92001 www.ti.com SNAS507B – FEBRUARY 2011 – REVISED APRIL 2012 There are 2 address setting pins, AS[1:0], that allow the device to occupy any one of 9 possible Interface Addresses on the bus. Block Access commands are provided to minimize the transfer overhead of larger data sets.
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LMP92001 SNAS507B – FEBRUARY 2011 – REVISED APRIL 2012 www.ti.
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LMP92001 www.ti.com SNAS507B – FEBRUARY 2011 – REVISED APRIL 2012 Pin Descriptions (continued) Name Pin ESD Structures Function C[1:4] 27:30 Asynchronous DAC output control digital inputs GPIO[0:7] 15:22 Digital I/O. CMOS Input or Open-Drain Output INT[1:2] 25:26 Interrupt outputs. Open-Drain, active LOW AREF 49 ADC reference DREF 51 DAC reference These devices have limited built-in ESD protection.
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LMP92001 SNAS507B – FEBRUARY 2011 – REVISED APRIL 2012 www.ti.com OPERATING CONDITIONS (1)(2) (continued) θJA 24°C/W θJC 2°C/W ELECTRICAL CHARACTERISTICS Unless otherwise noted, these specifications apply for VDD=4.75V to 5.5V, AREF=DREF=VDD, TA=25°C. Boldface limits are over the temperature range of −40°C ≤ TA ≤ 125°C unless otherwise noted. DAC input code range 48 to 4047. DAC output CL = 200 pF unless otherwise noted.
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LMP92001 www.ti.com SNAS507B – FEBRUARY 2011 – REVISED APRIL 2012 ELECTRICAL CHARACTERISTICS (continued) Unless otherwise noted, these specifications apply for VDD=4.75V to 5.5V, AREF=DREF=VDD, TA=25°C. Boldface limits are over the temperature range of −40°C ≤ TA ≤ 125°C unless otherwise noted. DAC input code range 48 to 4047. DAC output CL = 200 pF unless otherwise noted.
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LMP92001 SNAS507B – FEBRUARY 2011 – REVISED APRIL 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Unless otherwise noted, these specifications apply for VDD=4.75V to 5.5V, AREF=DREF=VDD, TA=25°C. Boldface limits are over the temperature range of −40°C ≤ TA ≤ 125°C unless otherwise noted. DAC input code range 48 to 4047. DAC output CL = 200 pF unless otherwise noted. Symbol Parameter Conditions Min Typ Max Units IOUT = 4mA 0.16 0.4 V IOUT = 6mA 0.23 0.
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LMP92001 www.ti.com SNAS507B – FEBRUARY 2011 – REVISED APRIL 2012 Figure 2.
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LMP92001 SNAS507B – FEBRUARY 2011 – REVISED APRIL 2012 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS ADC: INL VDD = 5V, AREF = 4.5V, TA = 25°C CREF.AEXT = 1, Single Channel Continuous Mode 2 2 1 1 INL (lsb) DNL (lsb) ADC: DNL VDD = 5V, AREF = 4.5V, TA = 25°C CREF.AEXT = 1, Single Channel Continuous Mode 0 0 -1 -1 -2 -2 0 1024 2048 0 3072 1024 2048 3072 CODE CODE Figure 3. Figure 4. DAC: DNL VDD = 5V, DREF = 4.5V, TA = 25°C CREF.DEXT = 1, RL = 100kΩ DAC: INL VDD = 5V, DREF = 4.
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LMP92001 www.ti.com SNAS507B – FEBRUARY 2011 – REVISED APRIL 2012 TYPICAL PERFORMANCE CHARACTERISTICS (continued) DAC: DNL vs Temperature VDD = 5V, DREF = 4.5V, CREF.DEXT = 1 DAC: INL vs Temperature VDD = 5V, DREF = 4.5V, CREF.DEXT = 1 4 4 3 3 Minimum INL Maximum INL 2 2 1 INL (lsb) DNL (lsb) 1 0 0 -1 -1 -2 -2 -3 -3 -4 -4 -50 5.0 -25 0 25 50 75 TEMPERATURE (°C) 100 125 -50 -25 0 25 50 75 TEMPERATURE (°C) 100 125 Figure 9. Figure 10.
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LMP92001 SNAS507B – FEBRUARY 2011 – REVISED APRIL 2012 www.ti.com REGISTER SET RESERVED registers in the map in REGISTER MAP should not be accessed for either read or write operations as this may lead to unpredictable behavior of the device. If writing to a RESERVED bit, user must write only 0, unless otherwise stated. REGISTER MAP Addr.
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LMP92001 www.ti.com SNAS507B – FEBRUARY 2011 – REVISED APRIL 2012 Addr.
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LMP92001 SNAS507B – FEBRUARY 2011 – REVISED APRIL 2012 www.ti.com Company ID Register: ID[7:0], default = 0x01 Product identification register, factory set. Device Version Register: VER[7:0], default = 0x10 Product identification register, factory set.
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LMP92001 www.ti.com SNAS507B – FEBRUARY 2011 – REVISED APRIL 2012 CONTROL REGISTERS General Configuration Register: CGEN[7:0], default = 0x00 Bx Name 7 RST Function 1 - RESETS all registers and self to POR value 6:3 - 2 TOD RESERVED 1 - disable I2C-compatible TIMEOUT. See I2C-Compatible Bus Reset 1 LCK 1 - to lock registers. Lockable registers are shown in the REGISTER MAP.
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LMP92001 SNAS507B – FEBRUARY 2011 – REVISED APRIL 2012 www.ti.
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LMP92001 www.ti.com SNAS507B – FEBRUARY 2011 – REVISED APRIL 2012 Bx Name 0 - Function RESERVED, must be 1 DATA REGISTERS All registers in this section require 16-bit I2C-compatible data transaction for both read and write operations. However, only lower 12 bits are stored. All data is assumed to be in the unsigned binary format, where the lowest value is represented by 0x000 and the highest value is represented by 0xFFF. ADC Output Data Register: ADCx[15:0], default 0x0000 The ADCx registers, x = 1.
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LMP92001 SNAS507B – FEBRUARY 2011 – REVISED APRIL 2012 www.ti.com BLOCK COMMANDS Block access functionality is discussed in Block Access.
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LMP92001 www.ti.com SNAS507B – FEBRUARY 2011 – REVISED APRIL 2012 In the expression above VREF is the reference voltage input to the internal ADC. VREF can be either externally applied at the AREF pin of the device, or be internally generated. Sampling Transient An instantaneous current will flow at the beginning of TRACK period which may lead to temporary disturbance of the input potential.
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LMP92001 SNAS507B – FEBRUARY 2011 – REVISED APRIL 2012 www.ti.com ADC IDLE Write CTRIG while CGEN.STRT=0 Write CGEN.STRT=1 N CGEN.LCK==1 Y set SGEN.BUSY=1 x=0 x=x+1 CAD(1|2|3).ENx==1 N Y set analog input MUX to channel x acquire signal tTRACK period convert input signal tHOLD period update ADCx register N x==17 Y set SGEN.BUSY=0 Figure 15.
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LMP92001 www.ti.com SNAS507B – FEBRUARY 2011 – REVISED APRIL 2012 Reference By default the ADC operates from the external reference voltage applied at AREF pin of the device. Due to the architecture of the ADC the DC current flowing into the AREF input is zero during conversion. However, the transient currents during the conversion can be significant. The user can enable the internal reference generator and apply its output to the ADC VREF. This operation is described in CONTROL REGISTERS.
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LMP92001 SNAS507B – FEBRUARY 2011 – REVISED APRIL 2012 www.ti.com x=1..3 SHIL Hx CINH EHx CINL ELy SLOL Ly INT1 y=1..3 x=9..11 SHIL Hx CINH EHx CINL ELy SLOL Ly INT2 y=9..11 Register bit Device Pin Register Figure 17. Interrupt System PROGRAMMABLE ANALOG OUTPUT SUBSYSTEM This subsystem consists of 12 identical DACs whose output is a function of user programmable registers DACx. This functionality is described in DAC Core.
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LMP92001 www.ti.com SNAS507B – FEBRUARY 2011 – REVISED APRIL 2012 VREF R R VDD R DACx 12 DECODER Buffer VOUTx R w(R) = 120k R 0 1 PD Figure 18. DAC Core Typical DAC core output VOUTx as a function of the DACx input , x=1...12, can be expressed as: DACx VOUTx = VREF x 4096 Reference By default the DACs operate from the external reference voltage applied at the DREF pin of the device.
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LMP92001 SNAS507B – FEBRUARY 2011 – REVISED APRIL 2012 www.ti.com VDD Cy 1 0 0 0 DAC Core x OUTx 1 1 PD pin:Cy Register bit CDAC:OFF Register CDAC OLVL OFF Device Pin Figure 19. Asynchronous Output Control Note that CDAC.OFF affects all OUTx, whereas Cy affects only channels assigned to it. The correspondence between Cy control inputs and OUTx outputs is governed by the CDAC.GANG bit and is outlined in Table 1. Table 1.
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LMP92001 www.ti.com SNAS507B – FEBRUARY 2011 – REVISED APRIL 2012 NOTE Internal reference drive must be disabled when corresponding external reference is applied; e.g., set CREF.AEXT=1 when applying external AREF. AREF DREF 1 To ADC VREF input x1 0 1 Reference Block PD To DACx VREF inputs x1 0 Register bit Register Device Pin CREF AEXT DEXT Figure 20. Reference Select Function GENERAL PURPOSE I/O The GPIO[7:0] port is memory mapped to registers SGPI and CGPO.
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LMP92001 SNAS507B – FEBRUARY 2011 – REVISED APRIL 2012 www.ti.com GPIOx SGPI GPIx 1 Register bit 0 Register Device Pin CGPO GPOx Figure 21. GPIO Functionality SERIAL INTERFACE The serial interface provides user access to internal CONTROL and DATA registers that govern the operation of the device. Interface functionality is compatible with I2C “Standard” and “Fast” modes. The device operates as the slave only.
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LMP92001 www.ti.com SNAS507B – FEBRUARY 2011 – REVISED APRIL 2012 SDA S SCL A6 A5 A1 A0 R/W A/A D7 D0 A/A C 1 2 6 7 8 9 1 8 9 Slave Address Byte Start Stop Data Byte by master by slave P D0 A/A 8 9 Sr by master or by slave Repeated Start Figure 22. General I2C-Compatible Protocol Table 2 lists all conditions defined by the I2C-compatible specification and supported by this device. All following bus descriptions will refer to the Symbols listed in the table. Table 2.
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LMP92001 SNAS507B – FEBRUARY 2011 – REVISED APRIL 2012 S A[6:0] www.ti.com W A Ar[7:0] A D[7:0] A Internal Register Address Interface Address D[7:0] A P Data by slave Figure 24. I2C-Compatible WRITE Access Protocol Device Address Interface Address of the device can be set via 2 pins: AS0 and AS1. Each address setting pin recognizes 3 levels: LOW=GND, HIGH=VDD and MID=VDD/2. All possible Interface Addresses are listed in Table 3 below: Table 3.
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LMP92001 www.ti.com SNAS507B – FEBRUARY 2011 – REVISED APRIL 2012 S A[6:0] W A Interface Address BLK0 A Sr Block Command A[6:0] R A D[7:0] Interface Address A D[7:0] A P 24 bytes of Data by master by slave Figure 26. Block Command READ Access S A[6:0] W A Interface Address BLK0 Block Command A D[7:0] A D[7:0] A P 24 bytes of Data by master by slave Figure 27.
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LMP92001 SNAS507B – FEBRUARY 2011 – REVISED APRIL 2012 www.ti.com Application Circuit Example 5V 0.01 0.1 10 PF + 499 VDD AREF DREF 10k Resulting Device Interface Address: 0x46 NOTE: In this application CREF is at default value LM4050-4.1 0.01 0.1 10 PF + 48V AS1 222k AS0 10k IN1 3.3V 1n 4-bit output from µC 10k 5V C[4:1] 3.33k IN2 LM8640 1n Details of Current Sense Omitted 3.3V LMP92001 12V 3.33k PC 10k 10k 10k LM8262 OUT1 10k To Analog Input SCL SDA 10k INT2 INT1 4.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMP92001SQE/NOPB WQFN NJY 54 250 178.0 16.4 5.8 10.3 1.0 12.0 16.0 Q1 LMP92001SQX/NOPB WQFN NJY 54 2000 330.0 16.4 5.8 10.3 1.0 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMP92001SQE/NOPB WQFN NJY LMP92001SQX/NOPB WQFN NJY 54 250 213.0 191.0 55.0 54 2000 367.0 367.0 38.
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PACKAGE OUTLINE NJY0054A WQFN SCALE 2.000 WQFN 5.6 5.4 B A PIN 1 INDEX AREA 0.5 0.3 0.3 0.2 10.1 9.9 DETAIL OPTIONAL TERMINAL TYPICAL 0.8 MAX C SEATING PLANE 2X 4 SEE TERMINAL DETAIL 3.51±0.1 19 (0.1) 27 28 18 50X 0.5 7.5±0.1 2X 8.5 1 45 54 PIN 1 ID (OPTIONAL) 46 54X 54X 0.5 0.3 0.3 0.2 0.1 0.05 C A C B 4214993/A 07/2013 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2.
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EXAMPLE BOARD LAYOUT NJY0054A WQFN WQFN (3.51) SYMM 54X (0.6) 54 54X (0.25) SEE DETAILS 46 1 45 50X (0.5) (7.5) SYMM (9.8) (1.17) TYP 2X (1.16) 28 18 ( 0.2) TYP VIA 19 27 (1) TYP (5.3) LAND PATTERN EXAMPLE SCALE:8X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND METAL SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) METAL SOLDER MASK DEFINED SOLDER MASK DETAILS 4214993/A 07/2013 NOTES: (continued) 4.
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EXAMPLE STENCIL DESIGN NJY0054A WQFN WQFN SYMM METAL TYP (0.855) TYP 46 54 54X (0.6) 54X (0.25) 1 45 50X (0.5) (1.17) TYP SYMM (9.8) 12X (0.97) 18 28 19 27 12X (1.51) (5.3) SOLDERPASTE EXAMPLE BASED ON 0.125mm THICK STENCIL EXPOSED PAD 67% PRINTED SOLDER COVERAGE BY AREA SCALE:10X 4214993/A 07/2013 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.
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