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LP2995

DDQ

REF

1.25V

SENSE

GND

50PF

DDQ

2.5V

1.25V

220PF

0.1PF

LP2995

www.ti.com

SNVS190M –FEBRUARY 2002–REVISED MARCH 2013

LP2995 DDR Termination Regulator

Check for Samples: LP2995

FEATURES

DESCRIPTION

The LP2995 linear regulator is designed to meet the

• Low Output Voltage Offset

JEDEC SSTL-2 and SSTL-3 specifications for

• Works with +5v, +3.3v and 2.5v Rails

termination of DDR-SDRAM. The device contains a

• Source and Sink Current

high-speed operational amplifier to provide excellent

response to load transients. The output stage

• Low External Component Count

prevents shoot through while delivering 1.5A

• No External Resistors Required

continuous current and transient peaks up to 3A in

• Linear Topology

the application as required for DDR-SDRAM

termination. The LP2995 also incorporates a V

SENSE

• Available in SOIC-8, SO PowerPAD-8 or

pin to provide superior load regulation and a V

REF

WQFN-16 Packages

output as a reference for the chipset and DDR

• Low Cost and Easy to Use

DIMMS.

WHITE SPACE

APPLICATIONS

WHITE SPACE

• DDR Termination Voltage

• SSTL-2

WHITE SPACE

• SSTL-3

WHITE SPACE

Typical Application Circuit

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (22 pages)

PAGE 1
LP2995 www.ti.com SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013 LP2995 DDR Termination Regulator Check for Samples: LP2995 FEATURES DESCRIPTION • • • • • • • The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.
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LP2995 SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013 www.ti.com 4 5 VDDQ N/C GND Figure 1. SOIC-8 (D0008A) Package Top View 16 15 14 13 1 12 PVIN 11 PVIN 2 GND N/C 3 10 AVIN N/C 4 9 N/C 5 6 7 8 Figure 2. NHP- 16 Package Top View NC 1 GND 2 VSENSE 3 VREF N/C VREF VTT 6 AVIN VREF 3 VDDQ 7 PVIN VSENSE VTT 8 VTT N/C 1 2 VSENSE NC GND N/C Connection Diagram 8 VTT GND 4 7 PVIN 6 AVIN 5 VDDQ Figure 3.
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LP2995 www.ti.com SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) AVIN to GND −0.3V to +6V PVIN to GND -0.3V to AVIN VDDQ (3) −0.3V to +6V −65°C to +150°C Storage Temp.
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LP2995 SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics VIN Iq vs (25°C) Iq vs Temperature ( VIN = 2.5V) 260 800 700 255 600 250 Iq (PA) Iq (PA) 500 400 245 300 240 200 235 100 2 2.5 3 VIN 3.5 4 4.5 5 0 5.5 25 50 75 100 VIN (VOLTS) TEMPERATURE (oC) Figure 4. Figure 5. Iq vs (0, 25, 85, and 125°C) VREF vs IREF 1.26 1050 125 1.255 900 125oC 1.25 1.245 VREF (V) Iq (PA) 750 600 0oC 450 1.24 1.235 1.23 1.225 300 1.22 150 1.
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LP2995 www.ti.com SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Maximum Output Current (Sourcing) vs VIN (VDDQ = 2.5) VTT vs IOUT 1.25 3.5 1.245 3 2.5 OUTPUT CURRENT (A) VTT (V) 1.24 1.235 1.23 2 1.5 1 1.225 1.22 -100 -75 0.5 0 -50 -25 0 25 50 75 100 2 IOUT (mA) 2.5 3 3.5 4 4.5 5 5.5 VIN (V) Figure 10. Figure 11. Maximum Output Current (Sinking) vs VIN (VDDQ = 2.5) 3.5 OUTPUT CRRENT (A) 3 2.5 2 1.5 1 0.5 0 2 2.5 3 3.
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LP2995 SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013 www.ti.
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LP2995 www.ti.com SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013 DETAILED DESCRIPTION The LP2995 is a linear bus termination regulator designed to meet the JEDEC requirements of SSTL-2 and SSTL-3. The LP2995 is capable of sinking and sourcing current at the output VTT, regulating the voltage to equal VDDQ / 2. A buffered reference voltage that also tracks VDDQ / 2 is generated on the VREF pin for providing a global reference to the DDR-SDRAM and Northbridge Chipset.
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LP2995 SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013 www.ti.com NOTE If remote load regulation is not used, then the VSENSE pin must still be connected to VTT. VREF VREF provides the buffered output of the internal reference voltage VDDQ / 2. This output should be used to provide the reference voltage for the Northbridge chipset and memory. Since these inputs are typically an extremely high impedance, there should be little current drawn from VREF.
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LP2995 www.ti.com SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013 performance are critical, although their cost is typically higher than any other capacitor. Capacitor recommendations for different application circuits can be seen in the accompanying application notes with supporting evaluation boards. Thermal Dissipation Since the LP2995 is a linear regulator any current flow from VTT will result in internal power dissipation generating heat.
PAGE 10
LP2995 SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013 www.ti.com 100 90 TJA (qC/W) 80 70 60 50 40 0 1 2 3 4 NUMBER OF VIAS Figure 15. WQFN-16 θJA vs # of Vias (4 Layer JEDEC Board)) Additional improvements in lowering the θJA can also be achieved with a constant airflow across the package. Maintaining the same conditions as above and utilizing the 2x2 via array, Figure 16 shows how the θJA varies with airflow.
PAGE 11
LP2995 www.ti.com SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013 For SSTL-3 and other applications it may be desirable to change internal reference voltage scaling from VDDQ * 0.5. An external resistor in series with the VDDQ pin can be used to lower the reference voltage. Internally two 50 kΩ resistors set the output VTT to be equal to VDDQ * 0.5. The addition of a 11.1 kΩ external resistor will change the internal reference voltage causing the two outputs to track VDDQ * 0.45.
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LP2995 SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision L (March 2013) to Revision M • 12 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LP2995LQ/NOPB WQFN NHP 16 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LP2995MRX SO Power PAD DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LP2995MRX/NOPB SO Power PAD DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP2995LQ/NOPB WQFN NHP 16 1000 213.0 191.0 55.0 LP2995MRX SO PowerPAD DDA 8 2500 367.0 367.0 35.0 LP2995MRX/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0 LP2995MX SOIC D 8 2500 367.0 367.0 35.0 LP2995MX/NOPB SOIC D 8 2500 367.0 367.0 35.
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MECHANICAL DATA DDA0008A MRA08A (Rev D) www.ti.
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MECHANICAL DATA NHP0016A LQA16A (REV A) www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.