Datasheet
Table Of Contents
V
TT
LP2996
PV
IN
V
DDQ
V
REF
AV
IN
V
REF
=
1.25V
V
SENSE
GND
PF
+
+
+
V
DDQ
=
2.5V
V
DD
=
2.5V
V
TT
=
1.25V
220PF
SD
SD
0.01PF
LP2996-N
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SNOSA40J –NOVEMBER 2002–REVISED MARCH 2013
LP2996-N DDR Termination Regulator
Check for Samples: LP2996-N
1
FEATURES
DESCRIPTION
The LP2996-N linear regulator is designed to meet
2
• Source and Sink Current
the JEDEC SSTL-2 specifications for termination of
• Low Output Voltage Offset
DDR-SDRAM. The device contains a high-speed
• No External Resistors Required
operational amplifier to provide excellent response to
load transients. The output stage prevents shoot
• Linear Topology
through while delivering 1.5A continuous current and
• Suspend to Ram (STR) Functionality
transient peaks up to 3A in the application as
• Low External Component Count
required for DDR-SDRAM termination. The LP2996-N
also incorporates a V
SENSE
pin to provide superior
• Thermal Shutdown
load regulation and a V
REF
output as a reference for
• Available in SOIC-8, SO PowerPAD-8 or
the chipset and DIMMs.
WQFN-16 packages
An additional feature found on the LP2996-N is an
active low shutdown (SD) pin that provides Suspend
APPLICATIONS
To RAM (STR) functionality. When SD is pulled low
• DDR-I and DDR-II Termination Voltage
the V
TT
output will tri-state providing a high
• SSTL-2 and SSTL-3 Termination
impedance output, but, V
REF
will remain active. A
power savings advantage can be obtained in this
• HSTL Termination
mode through lower quiescent current.
Typical Application Circuit
1
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.