Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - power management - special purpose 320 µA SOIC 8

LP2996

DDQ

REF

1.25V

SENSE

GND

PF

DDQ

2.5V

1.25V

220PF

0.01PF

LP2996-N

www.ti.com

SNOSA40J –NOVEMBER 2002–REVISED MARCH 2013

LP2996-N DDR Termination Regulator

Check for Samples: LP2996-N

FEATURES

DESCRIPTION

The LP2996-N linear regulator is designed to meet

• Source and Sink Current

the JEDEC SSTL-2 specifications for termination of

• Low Output Voltage Offset

DDR-SDRAM. The device contains a high-speed

• No External Resistors Required

operational amplifier to provide excellent response to

load transients. The output stage prevents shoot

• Linear Topology

through while delivering 1.5A continuous current and

• Suspend to Ram (STR) Functionality

transient peaks up to 3A in the application as

• Low External Component Count

required for DDR-SDRAM termination. The LP2996-N

also incorporates a V

SENSE

pin to provide superior

• Thermal Shutdown

load regulation and a V

REF

output as a reference for

• Available in SOIC-8, SO PowerPAD-8 or

the chipset and DIMMs.

WQFN-16 packages

An additional feature found on the LP2996-N is an

active low shutdown (SD) pin that provides Suspend

APPLICATIONS

To RAM (STR) functionality. When SD is pulled low

• DDR-I and DDR-II Termination Voltage

the V

output will tri-state providing a high

• SSTL-2 and SSTL-3 Termination

impedance output, but, V

REF

will remain active. A

power savings advantage can be obtained in this

• HSTL Termination

mode through lower quiescent current.

Typical Application Circuit

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (26 pages)

PAGE 1
LP2996-N www.ti.com SNOSA40J – NOVEMBER 2002 – REVISED MARCH 2013 LP2996-N DDR Termination Regulator Check for Samples: LP2996-N FEATURES DESCRIPTION • • • • • • • • The LP2996-N linear regulator is designed to meet the JEDEC SSTL-2 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.
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LP2996-N SNOSA40J – NOVEMBER 2002 – REVISED MARCH 2013 www.ti.com 4 3 GND 2 N/C SD N/C Connection Diagram 5 1 16 N/C 6 15 VREF VDDQ 7 VSENSE 14 N/C VTT VTT 13 12 N/C 9 10 11 N/C AVIN PVIN 8 1 8 VTT SD VSENSE 2 7 PVIN 3 6 VREF 4 5 AVIN VDDQ Figure 2. SOIC-8 Layout PVIN GND GND GND 1 8 VTT SD VSENSE 2 7 PVIN 3 6 VREF 4 5 AVIN VDDQ GND Figure 1. WQFN-16 Layout (Top View) Figure 3.
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LP2996-N www.ti.com SNOSA40J – NOVEMBER 2002 – REVISED MARCH 2013 Operating Range Junction Temp. Range (1) 0°C to +125°C AVIN to GND 2.2V to 5.5V PVIN Supply Voltage 0 to AVIN SD Input Voltage 0 to AVIN (1) At elevated temperatures, devices must be derated based on thermal resistance. The device in the SOIC-8 package must be derated at θJA = 151.2° C/W junction to ambient with no heat sink.
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LP2996-N SNOSA40J – NOVEMBER 2002 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics Iq vs AVIN 1050 350 900 300 750 250 600 IQ (uA) IQ (uA) Iq vs AVIN in SD 400 200 450 150 300 100 150 50 0 2 2.5 3 3.5 4 4.5 5 5.5 2 2.5 3 3.5 4 4.5 AVIN (V) AVIN (V) Figure 4. Figure 5. VIH and VIL 5 5.5 20 30 VREF vs IREF 4 1.40 3.5 1.35 3 VREF (V) VSD (V) 1.30 2.5 2 1.25 1.20 1.5 1.15 1 0.5 2 2.5 3 3.5 4 4.5 5 1.10 -30 5.
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LP2996-N www.ti.com SNOSA40J – NOVEMBER 2002 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VTT vs VDDQ Iq vs AVIN in SD Temperature 400 3 350 2.5 0oC 300 IQ (uA) VTT (V) 2 1.5 125oC 250 200 1 150 0.5 100 50 0 0 1 2 3 4 5 2 6 2.5 3 3.5 4 4.5 5 5.5 AV IN (V) VDDQ (V) Figure 10. Figure 11. Iq vs AVIN Temperature Maximum Sourcing Current vs AVIN (VDDQ = 2.5V, PVIN = 1.8V) 1.4 1050 85oC 1.
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LP2996-N SNOSA40J – NOVEMBER 2002 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Maximum Sourcing Current vs AVIN (VDDQ = 1.8V, PVIN = 1.8V) 3.0 1.4 2.8 1.2 2.6 1 OUTPUT CURRENT (A) OUTPUT CURRENT (A) Maximum Sinking Current vs AVIN (VDDQ = 2.5V) 2.4 2.2 2.0 1.8 0.8 0.6 0.4 0.2 1.6 0 2 2.5 3 3.5 4 4.5 5 5.5 2 2.5 3 3.5 AVIN (V) 4 4.5 5 5.5 AVIN (V) Figure 16. Figure 17. Maximum Sinking Current vs AVIN (VDDQ = 1.
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LP2996-N www.ti.com SNOSA40J – NOVEMBER 2002 – REVISED MARCH 2013 Description The LP2996-N is a linear bus termination regulator designed to meet the JEDEC requirements of SSTL-2. The output, VTT is capable of sinking and sourcing current while regulating the output voltage equal to VDDQ / 2. The output stage has been designed to maintain excellent load regulation while preventing shoot through.
PAGE 8
LP2996-N SNOSA40J – NOVEMBER 2002 – REVISED MARCH 2013 www.ti.com VSENSE The purpose of the sense pin is to provide improved remote load regulation. In most motherboard applications the termination resistors will connect to VTT in a long plane. If the output voltage was regulated only at the output of the LP2996-N then the long trace will cause a significant IR drop resulting in a termination voltage lower at one end of the bus than the other.
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LP2996-N www.ti.com SNOSA40J – NOVEMBER 2002 – REVISED MARCH 2013 COMPONENT SELECTIONS INPUT CAPACITOR The LP2996-N does not require a capacitor for input stability, but it is recommended for improved performance during large load transients to prevent the input rail from dropping. The input capacitor should be located as close as possible to the PVIN pin. Several recommendations exist dependent on the application required. A typical value recommended for AL electrolytic capacitors is 50 µF.
PAGE 10
LP2996-N SNOSA40J – NOVEMBER 2002 – REVISED MARCH 2013 www.ti.com 180 170 160 150 SOP Board TJA 140 130 120 110 JEDEC Board 100 90 80 0 200 400 600 800 1000 AIRFLOW (Linear Feet per Minute) Figure 21. θJA vs Airflow (SOIC-8) Additional improvements can be made by the judicious use of vias to connect the part and dissipate heat to an internal ground plane. Using larger traces and more copper on the top side of the board can also help.
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LP2996-N www.ti.com SNOSA40J – NOVEMBER 2002 – REVISED MARCH 2013 51 50 qJA (oC/W) 49 48 47 46 45 0 100 200 300 400 500 600 AIRFLOW (Linear Feet Per Minute) Figure 23. θJA vs Airflow Speed (JEDEC Board with 4 Vias) Optimizing the θJA and placing the LP2996-N in a section of a board exposed to lower ambient temperature allows the part to operate with higher power dissipation.
PAGE 12
LP2996-N SNOSA40J – NOVEMBER 2002 – REVISED MARCH 2013 www.ti.com LP2996 VREF = 1.25V VREF SD SD + CREF VDDQ = 2.5V VDDQ VDD = 2.5V AVIN VSENSE PVIN VTT + VTT = 1.25V + GND CIN COUT Figure 24. Recommended SSTL-2 Implementation If power dissipation or efficiency is a major concern then the LP2996-N has the ability to operate on split power rails. The output stage (PVIN) can be operated on a lower rail such as 1.8V and the analog circuitry (AVIN) can be connected to a higher rail such as 2.
PAGE 13
LP2996-N www.ti.com SNOSA40J – NOVEMBER 2002 – REVISED MARCH 2013 DDR-II APPLICATIONS With the separate VDDQ pin and an internal resistor divider it is possible to use the LP2996-N in applications utilizing DDR-II memory. Figure 25 and Figure 26 show several implementations of recommended circuits with output curves displayed in the Typical Performance Characteristics. Figure 25 shows the recommended circuit configuration for DDR-II applications. The output stage is connected to the 1.
PAGE 14
LP2996-N SNOSA40J – NOVEMBER 2002 – REVISED MARCH 2013 www.ti.com LP2996 VDDQ VDDQ VDD AVIN VTT VTT R1 PVIN + VSENSE COUT + GND CIN R2 Figure 29. Increasing VTT by Level Shifting Conversely, the R2 resistor can be placed between VSENSE and VDDQ to shift the VTT output lower than the internal reference voltage of VDDQ/2.
PAGE 15
LP2996-N www.ti.com SNOSA40J – NOVEMBER 2002 – REVISED MARCH 2013 OUTPUT CAPACITOR SELECTION For applications utilizing the LP2996-N to terminate SSTL-2 I/O signals the typical application circuit shown in Figure 30 can be implemented. LP2996 VREF = 1.25V VREF SD SD + VDDQ = 2.5V VDDQ VDD = 2.5V AVIN 0.01PF VSENSE VTT PVIN + VTT = 1.25V + GND PF 220PF Figure 32. Typical SSTL-2 Application Circuit This circuit permits termination in a minimum amount of board space and component count.
PAGE 16
LP2996-N SNOSA40J – NOVEMBER 2002 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision I (March 2013) to Revision J • 16 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line.
PAGE 19
PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LP2996LQ/NOPB WQFN NHP 16 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LP2996LQX/NOPB WQFN NHP 16 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LP2996MRX SO Power PAD DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP2996LQ/NOPB WQFN NHP 16 1000 213.0 191.0 55.0 LP2996LQX/NOPB WQFN NHP 16 4500 367.0 367.0 35.0 LP2996MRX SO PowerPAD DDA 8 2500 367.0 367.0 35.0 LP2996MRX/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0 LP2996MX/NOPB SOIC D 8 2500 367.0 367.0 35.
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MECHANICAL DATA DDA0008A MRA08A (Rev D) www.ti.
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MECHANICAL DATA NHP0016A LQA16A (REV A) www.ti.
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