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LP2997

DDQ

REF

0.9V

SENSE

GND

= 2.5V

= 0.9V

DDQ

= 1.8V

OUT

REF

LP2997

www.ti.com

SNVS295F –MAY 2004–REVISED APRIL 2013

LP2997 DDR-II Termination Regulator

Check for Samples: LP2997

FEATURES

DESCRIPTION

The LP2997 linear regulator is designed to meet the

• Source and Sink Current

JEDEC SSTL-18 specifications for termination of

• Low Output Voltage Offset

DDR-II memory. The device contains a high-speed

• No External Resistors Required

operational amplifier to provide excellent response to

load transients. The output stage prevents shoot

• Linear Topology

through while delivering 500mA continuous current

• Suspend to Ram (STR) Functionality

and transient peaks up to 900mA in the application as

• Low External Component Count

required for DDR-II SDRAM termination. The LP2997

also incorporates a V

SENSE

pin to provide superior

• Thermal Shutdown

load regulation and a V

REF

output as a reference for

• Available in SOIC-8, SO PowerPAD-8 Packages

the chipset and DIMMs.

An additional feature found on the LP2997 is an

APPLICATIONS

active low shutdown (SD) pin that provides Suspend

• DDR-II Termination Voltage

To RAM (STR) functionality. When SD is pulled low

• SSTL-18 Termination

the V

output will tri-state providing a high

impedance output, but, V

REF

will remain active. A

power savings advantage can be obtained in this

mode through lower quiescent current.

Typical Application Circuit

Figure 1. Typical Application Circuit

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (19 pages)

PAGE 1
LP2997 www.ti.com SNVS295F – MAY 2004 – REVISED APRIL 2013 LP2997 DDR-II Termination Regulator Check for Samples: LP2997 FEATURES DESCRIPTION • • • • • • • • The LP2997 linear regulator is designed to meet the JEDEC SSTL-18 specifications for termination of DDR-II memory. The device contains a high-speed operational amplifier to provide excellent response to load transients.
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LP2997 SNVS295F – MAY 2004 – REVISED APRIL 2013 www.ti.com Connection Diagram GND 1 8 VTT SD VSENSE 2 7 PVIN 3 6 VREF 4 5 AVIN VDDQ GND Figure 2. SO PowerPAD-8 Layout See Package Number DDA (R-PDSO-G8) GND 1 8 VTT SD VSENSE 2 7 PVIN 3 6 VREF 4 5 AVIN VDDQ Figure 3. SOIC-8 Layout See Package Number D0008A PIN DESCRIPTIONS SOIC-8 Pin or SO PowerPAD-8 Pin Name 1 GND 2 SD 3 VSENSE Function Ground Shutdown Feedback pin for regulating VTT.
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LP2997 www.ti.com SNVS295F – MAY 2004 – REVISED APRIL 2013 Electrical Characteristics Specifications with standard typeface are for TJ = 25°C and limits in boldface type apply over the full Operating Temperature Range (TJ = 0°C to +125°C) (1). Unless otherwise specified, AVIN = 2.5V, PVIN = 1.8V, VDDQ = 1.8V. Symbol VREF Parameter VREF Voltage Conditions PVIN = VDDQ = 1.7V PVIN = VDDQ = 1.8V PVIN = VDDQ = 1.9V Min Typ Max Units 0.837 0.887 0.936 0.860 0.910 0.959 0.887 0.937 0.
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LP2997 SNVS295F – MAY 2004 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics Iq vs AVIN 1050 350 900 300 750 250 600 IQ (uA) IQ (uA) Iq vs AVIN in SD 400 200 450 150 300 100 150 50 0 2 2.5 3 3.5 4 4.5 5 5.5 2 2.5 3 3.5 4 AVIN (V) AVIN (V) Figure 4. Figure 5. VIH and VIL 4.5 5 5.5 VREF vs VDDQ 4 3 3.5 2.5 3 VREF (V) VSD (V) 2 2.5 2 1.5 1 1.5 0.5 1 0.5 0 2 2.5 3 3.5 4 4.5 5 5.5 0 1 2 3 4 AVIN (V) VDDQ (V) Figure 6. Figure 7.
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LP2997 www.ti.com SNVS295F – MAY 2004 – REVISED APRIL 2013 Typical Performance Characteristics (continued) Maximum Sourcing Current vs AVIN (VDDQ = 1.8V, PVIN = 1.8V) Iq vs AVIN Temperature 1.4 1050 85oC 1.2 IQ (uA) 750 OUTPUT CURRENT (A) 900 25oC 600 0oC 450 300 1 0.8 0.6 0.4 0.2 150 0 0 2 2.5 3 3.5 4 4.5 5 2 5.5 2.5 AVIN (V) 3 3.5 4 4.5 5 5.5 AVIN (V) Figure 10. Figure 11. Maximum Sinking Current vs AVIN (VDDQ = 1.8V) 2.4 OUTPUT CURRENT (A) 2.2 2 1.8 1.6 1.4 1.2 1 2 2.
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LP2997 SNVS295F – MAY 2004 – REVISED APRIL 2013 www.ti.com DESCRIPTION The LP2997 is a linear bus termination regulator designed to meet the JEDEC requirements of SSTL-18. The output, VTT is capable of sinking and sourcing current while regulating the output voltage equal to VDDQ / 2. The output stage has been designed to maintain excellent load regulation while preventing shoot through. The LP2997 also incorporates two distinct power rails that separates the analog circuitry from the power output stage.
PAGE 7
LP2997 www.ti.com SNVS295F – MAY 2004 – REVISED APRIL 2013 OUTPUT CAPACITOR The LP2997 has been designed to be insensitive of output capacitor size or ESR (Equivalent Series Resistance). This allows the flexibility to use any capacitor desired. The choice for output capacitor will be determined solely on the application and the requirements for load transient response of VTT. As a general recommendation the output capacitor should be sized above 100 µF with a low ESR for SSTL applications with DDR-SDRAM.
PAGE 8
LP2997 SNVS295F – MAY 2004 – REVISED APRIL 2013 www.ti.com Additional improvements can be made by the judicious use of vias to connect the part and dissipate heat to an internal ground plane. Using larger traces and more copper on the top side of the board can also help. With careful layout it is possible to reduce the θJA further than the nominal values shown in Figure 13.
PAGE 9
LP2997 www.ti.com SNVS295F – MAY 2004 – REVISED APRIL 2013 PCB Layout Considerations 1. The input capacitor for the power rail should be placed as close as possible to the PVIN pin. 2. VSENSE should be connected to the VTT termination bus at the point where regulation is required. For motherboard applications an ideal location would be at the center of the termination bus. 3. VDDQ can be connected remotely to the VDDQ rail input at either the DIMM or the Chipset.
PAGE 10
LP2997 SNVS295F – MAY 2004 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision E (April 2013) to Revision F • 10 Page Changed layout of National Data Sheet to TI format ............................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line.
PAGE 13
PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LP2997MRX SO Power PAD DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LP2997MRX/NOPB SO Power PAD DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LP2997MX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.
PAGE 14
PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP2997MRX SO PowerPAD DDA 8 2500 367.0 367.0 35.0 LP2997MRX/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0 LP2997MX/NOPB SOIC D 8 2500 367.0 367.0 35.
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MECHANICAL DATA DDA0008A MRA08A (Rev D) www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.