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LP2998

DDQ

REF

SENSE

GND

OUT

REF

2.5V

DDQ

1.8V

0.9V

REF

0.9V

LP2998

www.ti.com

SNVS521I –DECEMBER 2007–REVISED APRIL 2013

LP2998 DDR-I and DDR-II Termination Regulator

Check for Samples: LP2998

FEATURES

DESCRIPTION

The LP2998 linear regulator is designed to meet

• Source and Sink Current

JEDEC SSTL-2 and JEDEC SSTL-18 specifications

• Low Output Voltage Offset

for termination of DDR1-SDRAM and DDR-II

• No External Resistors Required

memory. The device contains a high-speed

operational amplifier to provide excellent response to

• Linear Topology

load transients. The output stage prevents shoot

• Suspend to Ram (STR) Functionality

through while delivering 1.5A continuous current as

• Low External Component Count

required for DDR1-SDRAM termination, and 0.5A

continuous current as required for DDR-II termination.

• Thermal Shutdown

The LP2998 also incorporates a V

SENSE

pin to provide

• Available in SOIC-8, SO PowerPAD-8 Packages

superior load regulation and a V

REF

output as a

reference for the chipset and DIMMs.

APPLICATIONS

An additional feature found on the LP2998 is an

• DDR-I, DDR-II and DDR-III Termination Voltage

active low shutdown (SD) pin that provides Suspend

• SSTL-18 Termination

To RAM (STR) functionality. When SD is pulled low,

the V

output will tri-state providing a high

• SSTL-2 and SSTL-3 Termination

impedance output, while V

REF

remains active. A

• HSTL Termination

power savings advantage can be obtained in this

mode through lower quiescent current.

Typical Application Circuit

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (26 pages)

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LP2998 www.ti.com SNVS521I – DECEMBER 2007 – REVISED APRIL 2013 LP2998 DDR-I and DDR-II Termination Regulator Check for Samples: LP2998 FEATURES DESCRIPTION • • • • • • • • The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of DDR1-SDRAM and DDR-II memory. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.
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LP2998 SNVS521I – DECEMBER 2007 – REVISED APRIL 2013 www.ti.com Connection Diagrams Top View GND 1 8 VTT SD VSENSE 2 7 PVIN 3 6 VREF 4 5 AVIN VDDQ GND Figure 1. SO PowerPAD-8 Package See Package Number DDA0008A Top View GND 1 8 VTT SD VSENSE 2 7 PVIN 3 6 VREF 4 5 AVIN VDDQ Figure 2. SOIC-8 Package See Package Number D0008A Pin Descriptions SOIC-8 Pin or SO PowerPAD-8 Pin Name Function 1 GND 2 SD 3 VSENSE 4 VREF Buffered internal reference voltage of VDDQ /2.
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LP2998 www.ti.com SNVS521I – DECEMBER 2007 – REVISED APRIL 2013 Absolute Maximum Ratings (1) (2) AVIN to GND −0.3V to +6V PVIN to GND -0.3V to AVIN VDDQ (3) −0.3V to +6V Storage Temp.
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LP2998 SNVS521I – DECEMBER 2007 – REVISED APRIL 2013 www.ti.com Electrical Characteristics (continued) Specifications with standard typeface are for TJ = 25°C and limits in boldface type apply over the full Operating Temperature Range (TJ = -40°C to +125°C) (1). Unless otherwise specified, VIN = AVIN = PVIN = 2.5V. Parameter Test Conditions Min Typ Max Units VIN = VDDQ = 2.3V 1.120 1.159 1.190 V VIN = VDDQ = 2.5V 1.210 1.259 1.290 V VIN = VDDQ = 2.7V 1.320 1.359 1.
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LP2998 www.ti.com SNVS521I – DECEMBER 2007 – REVISED APRIL 2013 Electrical Characteristics (continued) Specifications with standard typeface are for TJ = 25°C and limits in boldface type apply over the full Operating Temperature Range (TJ = -40°C to +125°C) (1). Unless otherwise specified, VIN = AVIN = PVIN = 2.5V. Parameter IQ_SD Shutdown leakage current VIH Minimum Shutdown High Level VIL Maximum Shutdown Low Level Iv VTT leakage current in shutdown ISENSE TSD Test Conditions SD = 0V VTT = 1.
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LP2998 SNVS521I – DECEMBER 2007 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics Unless otherwise specified VIN = AVIN = PVIN = 2.5V Iq vs AVIN 1050 350 900 300 750 250 600 IQ (uA) IQ (uA) Iq vs AVIN in SD 400 200 450 150 300 100 150 50 0 2 2.5 3 3.5 4 4.5 5 5.5 2 2.5 3 3.5 AVIN (V) 4 4.5 5 5.5 AVIN (V) Figure 3. Figure 4. VIH and VIL VREF vs VDDQ 4 3 3.5 2.5 3 VREF (V) VSD (V) 2 2.5 2 1.5 1 1.5 0.5 1 0.5 0 2 2.5 3 3.5 4 4.5 5 5.
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LP2998 www.ti.com SNVS521I – DECEMBER 2007 – REVISED APRIL 2013 Typical Performance Characteristics (continued) Unless otherwise specified VIN = AVIN = PVIN = 2.5V Maximum Sourcing Current vs AVIN (VDDQ = 1.8V, PVIN = 1.8V) Iq vs AVIN over Temperature 1.4 1050 25oC IQ (PA) 750 1.2 OUTPUT CURRENT (A) 900 -40oC 600 85oC o 125 C 450 300 1 0.8 0.6 0.4 0.2 150 0 2 0 2.5 3 3.5 4 4.5 5 5.5 2 2.5 3 3.5 4 4.5 5 5.5 AVIN (V) Figure 9. Figure 10.
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LP2998 SNVS521I – DECEMBER 2007 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified VIN = AVIN = PVIN = 2.5V Maximum Sinking Current vs AVIN (VDDQ = 2.5V) Maximum Sourcing Current vs AVIN (VDDQ = 1.8V, PVIN = 3.3V) 3.0 3 2.8 OUTPUT CURRENT (A) OUTPUT CURRENT (A) 2.8 2.6 2.4 2.2 2.0 2.6 2.4 2.2 1.8 1.6 2 2 2.5 3 3.5 4 4.5 5 5.5 AVIN (V) 3.5 4 4.5 5 5.5 AVIN (V) Figure 15. 8 3 Figure 16.
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LP2998 www.ti.com SNVS521I – DECEMBER 2007 – REVISED APRIL 2013 Block Diagram VDDQ SD PVIN AVIN 50k VREF + - + 50k VTT VSENSE GND DETAILED DESCRIPTION The LP2998 is a linear bus termination regulator designed to meet the JEDEC requirements of SSTL-2 and SSTL-18. The output, VTT is capable of sinking and sourcing current while regulating the output voltage equal to VDDQ / 2. The output stage has been designed to maintain excellent load regulation while preventing shoot through.
PAGE 10
LP2998 SNVS521I – DECEMBER 2007 – REVISED APRIL 2013 www.ti.com Pin Descriptions AVIN AND PVIN AVIN and PVIN are the input supply pins for the LP2998. AVIN is used to supply all the internal control circuitry. PVIN, however, is used exclusively to provide the rail voltage for the output stage used to create VTT. These pins have the capability to work off separate supplies, under the condition that AVIN is always greater than or equal to PVIN.
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LP2998 www.ti.com SNVS521I – DECEMBER 2007 – REVISED APRIL 2013 OUTPUT CAPACITOR The LP2998 has been designed to be insensitive of output capacitor size or ESR (Equivalent Series Resistance). This allows the flexibility to use any capacitor desired. The choice for output capacitor will be determined solely on the application and the requirements for load transient response of VTT.
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LP2998 SNVS521I – DECEMBER 2007 – REVISED APRIL 2013 www.ti.com 180 170 160 150 SOP Board TJA 140 130 120 110 JEDEC Board 100 90 80 0 200 400 600 800 1000 AIRFLOW (Linear Feet per Minute) Figure 18. θJA vs Airflow (SOIC-8) Additional improvements can be made by the judicious use of vias to connect the part and dissipate heat to an internal ground plane. Using larger traces and more copper on the top side of the board can also help.
PAGE 13
LP2998 www.ti.com SNVS521I – DECEMBER 2007 – REVISED APRIL 2013 LP2998 VREF = 1.25V VREF SD SD + VDDQ VDDQ = 2.5V VDD = 2.5V CIN + AVIN VSENSE PVIN VTT CREF VTT = 1.25V + GND COUT Figure 19. Recommended SSTL-2 Implementation If power dissipation or efficiency is a major concern then the LP2998 has the ability to operate on split power rails (see Figure 20). The output stage (PVIN) can be operated on a lower rail such as 1.
PAGE 14
LP2998 SNVS521I – DECEMBER 2007 – REVISED APRIL 2013 www.ti.com DDR-II APPLICATIONS With the separate VDDQ pin and an internal resistor divider it is possible to use the LP2998 in applications utilizing DDR-II memory. Figure 22 and Figure 23 show several implementations of recommended circuits with output curves displayed in the Typical Performance Characteristics. Figure 22 shows the recommended circuit configuration for DDR-II applications. The output stage is connected to the 1.
PAGE 15
LP2998 www.ti.com SNVS521I – DECEMBER 2007 – REVISED APRIL 2013 LP2998 VDDQ VDDQ VDD VTT VTT AVIN R1 PVIN CIN + VSENSE + GND COUT R2 Figure 24. Increasing VTT by Level Shifting Conversely, the R2 resistor can be placed between VSENSE and VDDQ to shift the VTT output lower than the internal reference voltage of VDDQ/2.
PAGE 16
LP2998 SNVS521I – DECEMBER 2007 – REVISED APRIL 2013 www.ti.com OUTPUT CAPACITOR SELECTION For applications utilizing the LP2998 to terminate SSTL-2 I/O signals the typical application circuit shown in Figure 27 can be implemented. LP2998 + AVIN = 2.5V AVIN VDDQ = 1.8V VDDQ CREF VSENSE PVIN CIN VREF = 0.9V VREF SD SD VTT = 0.9V VTT + + GND COUT Figure 27. Typical SSTL-2 Application Circuit This circuit permits termination in a minimum amount of board space and component count.
PAGE 17
LP2998 www.ti.com SNVS521I – DECEMBER 2007 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision H (April 2013) to Revision I • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LP2998MAE/NOPB SOIC SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant D 8 250 178.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LP2998MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LP2998MRE/NOPB SO Power PAD DDA 8 250 178.0 12.4 6.5 5.4 2.0 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP2998MAE/NOPB SOIC D LP2998MAX/NOPB SOIC D 8 250 210.0 185.0 35.0 8 2500 367.0 367.0 35.0 LP2998MRE/NOPB SO PowerPAD DDA LP2998MRX/NOPB SO PowerPAD DDA 8 250 213.0 191.0 55.0 8 2500 367.0 367.0 35.
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MECHANICAL DATA DDA0008A MRA08A (Rev D) www.ti.
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