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LP38500-ADJ, LP38502-ADJ

www.ti.com

SNVS539F –NOVEMBER 2007–REVISED APRIL 2013

LP38500/2-ADJ, LP38500A/2A-ADJ 1.5A FlexCap Low Dropout Linear Regulator for 2.7V to

5.5V Inputs

Check for Samples: LP38500-ADJ, LP38502-ADJ

FEATURES

DESCRIPTION

TI's FlexCap LDO's feature unique compensation that

• FlexCap: Stable with Ceramic, Tantalum, or

allows the use of any type of output capacitor with no

Aluminum Capacitors

limits on minimum or maximum ESR. The LP38500/2

• Stable with 10 µF Input/output Capacitor

series of low-dropout linear regulators operates from

• Adjustable Output Voltage from 0.6V to 5V

a +2.7V to +5.5V input supply. These ultra low

dropout linear regulators respond very quickly to step

• Low Ground Pin Current

changes in load, which makes them suitable for low

• 25 nA Quiescent Current in Shutdown Mode

voltage microprocessor applications. Developed on a

• Ensured Output Current of 1.5A

CMOS process, (utilizing a PMOS pass transistor),

the LP38500/2 has low quiescent current that

• Available in DDPAK/TO-263, PFM, and WSON-8

changes little with load current.

Packages

Ground Pin Current: Typically 2 mA at 1.5A load

• Ensured V

ADJ

Accuracy of ±1.5% @ 25°C (A

current.

Grade)

• Ensured Accuracy of ±3.5% @ 25°C (STD)

Disable Mode: Typically 25 nA quiescent current

when the Enable pin is pulled low.

• Over-Temperature and Over-Current

Protection

Simplified Compensation: Stable with any type of

output capacitor, regardless of ESR.

• −40°C to +125°C Operating T

Range

• Enable Pin (LP38502)

Precision Output: "A" grade versions available with

1.5% V

ADJ

tolerance (25°C) and 3% over line, load

and temperature.

APPLICATIONS

• ASIC Power Supplies In:

– Printers, Graphics Cards, DVD Players

– Set Top Boxes, Copiers, Routers

• DSP and FPGA Power Supplies

• SMPS Regulator

• Conversion from 3.3V or 5V Rail

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (23 pages)

PAGE 1
LP38500-ADJ, LP38502-ADJ www.ti.com SNVS539F – NOVEMBER 2007 – REVISED APRIL 2013 LP38500/2-ADJ, LP38500A/2A-ADJ 1.5A FlexCap Low Dropout Linear Regulator for 2.7V to 5.5V Inputs Check for Samples: LP38500-ADJ, LP38502-ADJ FEATURES DESCRIPTION • TI's FlexCap LDO's feature unique compensation that allows the use of any type of output capacitor with no limits on minimum or maximum ESR. The LP38500/2 series of low-dropout linear regulators operates from a +2.7V to +5.5V input supply.
PAGE 2
LP38500-ADJ, LP38502-ADJ SNVS539F – NOVEMBER 2007 – REVISED APRIL 2013 www.ti.com Typical Application Circuit Connection Diagrams for DDPAK/TO-263 Package Figure 1. 5-Pin DDPAK/TO-263, Top View (LP38500TS-ADJ) See KTT0005B Package Figure 2. 5-Pin DDPAK/TO-263, Top View (LP38502TS-ADJ) See KTT0005B Package Connection Diagrams for PFM Package Figure 3. 5-Pin PFM, Top View (LP38500TJ-ADJ, LP38500ATJ-ADJ) See NDQ0005A Package 2 Submit Documentation Feedback Figure 4.
PAGE 3
LP38500-ADJ, LP38502-ADJ www.ti.com SNVS539F – NOVEMBER 2007 – REVISED APRIL 2013 PIN DESCRIPTIONS FOR DDPAK/TO-263 and PFM PACKAGES Pin # Designation Function EN Enable (LP38502 only). Pull high to enable the output, low to disable the output. This pin has no internal bias and must be either tied to the input voltage, or actively driven. N/C In the LP38500, this pin has no internal connections. It can be left floating or used for trace routing.
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LP38500-ADJ, LP38502-ADJ SNVS539F – NOVEMBER 2007 – REVISED APRIL 2013 www.ti.com Absolute Maximum Ratings (1) (2) −65°C to +150°C Storage Temperature Range Lead Temperature (Soldering, 5 sec.) 260°C ESD Rating (3) ±2 kV Power Dissipation (4) Internally Limited Input Pin Voltage (Survival) −0.3V to +6.0V Enable Pin Voltage (Survival) −0.3V to +6.0V Output Pin Voltage (Survival) −0.3V to +6.
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LP38500-ADJ, LP38502-ADJ www.ti.com SNVS539F – NOVEMBER 2007 – REVISED APRIL 2013 Electrical Characteristics LP38500/2–ADJ (continued) Unless otherwise specified: VIN = 3.3V, IOUT = 10 mA, CIN = 10 µF, COUT = 10 µF, VEN = VIN, VOUT = 1.8V. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation.
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LP38500-ADJ, LP38502-ADJ SNVS539F – NOVEMBER 2007 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics Unless otherwise specified: TJ = 25°C, VIN = 2.7V, VEN = VIN, CIN = 10 µF, COUT = 10 µF, IOUT = 10 mA, VOUT = 1.8V 6 Noise Density Noise Density Figure 7. Figure 8. IGND vs Load Current IGND(OFF) vs Temperature Figure 9. Figure 10. VADJ vs Temperature Dropout Voltage vs Load Current Figure 11. Figure 12.
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LP38500-ADJ, LP38502-ADJ www.ti.com SNVS539F – NOVEMBER 2007 – REVISED APRIL 2013 Typical Performance Characteristics (continued) Unless otherwise specified: TJ = 25°C, VIN = 2.7V, VEN = VIN, CIN = 10 µF, COUT = 10 µF, IOUT = 10 mA, VOUT = 1.8V VEN vs Temperature Turn-on Characteristics Figure 13. Figure 14. Turn-on Time Turn-on Time Figure 15. Figure 16. PSRR Figure 17.
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LP38500-ADJ, LP38502-ADJ SNVS539F – NOVEMBER 2007 – REVISED APRIL 2013 www.ti.com Block Diagrams (DDPAK/TO-263, PFM) Figure 18. LP38500-ADJ DDPAK/TO-263 Block Diagram Figure 19. LP38502-ADJ DDPAK/TO-263 Block Diagram Block Diagrams (WSON) Figure 20. LP38500-ADJ WSON Block Diagram Figure 21.
PAGE 9
LP38500-ADJ, LP38502-ADJ www.ti.com SNVS539F – NOVEMBER 2007 – REVISED APRIL 2013 APPLICATION INFORMATION EXTERNAL CAPACITORS The LP3850X requires that at least 10 µF (±20%) capacitors be used at the input and output pins located within one cm of the IC. Larger capacitors may be used without limit on size for both CIN and COUT.
PAGE 10
LP38500-ADJ, LP38502-ADJ SNVS539F – NOVEMBER 2007 – REVISED APRIL 2013 www.ti.com STABILITY AND PHASE MARGIN Any regulator which operates using a feedback loop must be compensated in such a way as to ensure adequate phase margin, which is defined as the difference between the phase shift and -180 degrees at the frequency where the loop gain crosses unity (0 dB). For most LDO regulators, the ESR of the output capacitor is required to create a zero to add enough phase lead to ensure stable operation.
PAGE 11
LP38500-ADJ, LP38502-ADJ www.ti.com SNVS539F – NOVEMBER 2007 – REVISED APRIL 2013 LOAD TRANSIENT RESPONSE Load transient response is defined as the change in regulated output voltage which occurs as a result of a change in load current. Many applications have loads which vary, and the control loop of the voltage regulator must adjust the current in the pass FET transistor in response to load current changes. For this reason, regulators with wider bandwidths often have better transient response.
PAGE 12
LP38500-ADJ, LP38502-ADJ SNVS539F – NOVEMBER 2007 – REVISED APRIL 2013 www.ti.com The external resistors which set the output voltage must also be located very near the IC with all connections directly tied via short traces to the pins of the IC (Kelvin connect). Do not connect the resistive divider to the load point or DC error will be induced.
PAGE 13
LP38500-ADJ, LP38502-ADJ www.ti.com SNVS539F – NOVEMBER 2007 – REVISED APRIL 2013 DROPOUT VOLTAGE The dropout voltage of a regulator is defined as the input-to-output differential required by the regulator to keep the output voltage within 2% of the nominal value. For CMOS LDOs, the dropout voltage is the product of the load current and the RDS(on) of the internal MOSFET pass element.
PAGE 14
LP38500-ADJ, LP38502-ADJ SNVS539F – NOVEMBER 2007 – REVISED APRIL 2013 www.ti.com Figure 26. θJA vs Copper Area for DDPAK/TO-263 Package As shown in the figure, increasing the copper area beyond 1.5 square inch produces very little improvement. HEATSINKING WSON PACKAGE The junction-to-ambient thermal resistance for the WSON-8 package is dependent on how much PCB copper is present to conduct heat away from the device.
PAGE 15
LP38500-ADJ, LP38502-ADJ www.ti.com SNVS539F – NOVEMBER 2007 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision E (April 2013) to Revision F • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
PAGE 16
PACKAGE OPTION ADDENDUM www.ti.
PAGE 17
PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 21-May-2013 Status (1) LP38502TSX-ADJ/NOPB ACTIVE Package Type Package Pins Package Drawing Qty DDPAK/ TO-263 KTT 5 500 Eco Plan Lead/Ball Finish (2) Pb-Free (RoHS Exempt) MSL Peak Temp Op Temp (°C) Device Marking (3) CU SN Level-3-245C-168 HR (4/5) -40 to 125 LP38502 TS-ADJ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
PAGE 18
PACKAGE MATERIALS INFORMATION www.ti.com 10-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device LP38500ASD-ADJ/NOPB Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant WSON NGS 8 1000 178.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1 LP38500ASDX-ADJ/NOP B WSON NGS 8 4500 330.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1 LP38500ATJ-ADJ/NOPB TO-263 NDQ 5 1000 330.0 24.4 10.6 15.4 2.45 12.0 24.
PAGE 19
PACKAGE MATERIALS INFORMATION www.ti.com 10-Sep-2013 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TO-263 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP38500ASD-ADJ/NOPB WSON NGS 8 1000 210.0 185.0 35.0 LP38500ASDX-ADJ/NOPB WSON NGS 8 4500 367.0 367.0 35.0 LP38500ATJ-ADJ/NOPB TO-263 NDQ 5 1000 367.0 367.0 35.
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MECHANICAL DATA NDQ0005A TJ5A (Rev F) www.ti.
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MECHANICAL DATA NGS0008C SDA08C (Rev A) www.ti.
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MECHANICAL DATA KTT0005B TS5B (Rev D) BOTTOM SIDE OF PACKAGE www.ti.
PAGE 23
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