Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - LDO voltage regulator Positive, fixed TO 252 3

LP38693

OUT

SNS

GND

1 PF *

OUT

LP38691

OUT

SNS

GND

1 PF *

OUT

LP38691, LP38693

www.ti.com

SNVS321K –JANUARY 2005–REVISED APRIL 2013

LP38691

LP38693 500mA Low Dropout CMOS Linear Regulators

Stable with Ceramic Output Capacitors

Check for Samples: LP38691, LP38693

FEATURES

DESCRIPTION

The LP38691/3 low dropout CMOS linear regulators

• All WSON Options are Available as AEC-Q100

provide tight output tolerance (2.0% typical),

Grade 1

extremely low dropout voltage (250 mV @ 500mA

• 2.0% Output Accuracy (25°C)

load current, V

OUT

= 5V), and excellent AC

• Low Dropout Voltage: 250 mV @ 500mA (typ,

performance utilizing ultra low ESR ceramic output

capacitors.

5V out)

• Wide Input Voltage Range (2.7V to 10V)

The low thermal resistance of the WSON, SOT-223

and PFM packages allow the full operating current to

• Precision (Trimmed) Bandgap Reference

be used even in high ambient temperature

• Ensured Specs for -40°C to +125°C

environments.

• 1µA Off-State Quiescent Current

The use of a PMOS power transistor means that no

• Thermal Overload Protection

DC base drive current is required to bias it allowing

• Foldback Current Limiting

ground pin current to remain below 100 µA

regardless of load current, input voltage, or operating

• PFM, SOT-223 and 6-Lead WSON Packages

temperature.

• Enable Pin (LP38693)

Dropout Voltage: 250 mV (typ) @ 500mA (typ. 5V

out).

APPLICATIONS

• Hard Disk Drives Ground Pin Current: 55 µA (typ) at full load.

• Notebook Computers

Precision Output Voltage: 2.0% (25°C) accuracy.

• Battery Powered Devices

• Portable Instrumentation

Typical Application Circuits

* Minimum value required for stability.

**WSON package devices only.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (27 pages)

PAGE 1
LP38691, LP38693 www.ti.com SNVS321K – JANUARY 2005 – REVISED APRIL 2013 LP38691 LP38693 500mA Low Dropout CMOS Linear Regulators Stable with Ceramic Output Capacitors Check for Samples: LP38691, LP38693 FEATURES DESCRIPTION • The LP38691/3 low dropout CMOS linear regulators provide tight output tolerance (2.0% typical), extremely low dropout voltage (250 mV @ 500mA load current, VOUT = 5V), and excellent AC performance utilizing ultra low ESR ceramic output capacitors.
PAGE 2
LP38691, LP38693 SNVS321K – JANUARY 2005 – REVISED APRIL 2013 www.ti.com Connection Diagrams VEN 1 N/C 2 5 GND VOUT 3 VIN 4 Figure 1. PFM (LP38691DT-X.X) – Top View See Package Number NDP0003B VIN 1 GND 2 N/C 3 Exposed Pad on Bottom (DAP) 6 VIN 5 4 Figure 2. SOT-223 (LP38693MP-X.X) – Top View See Package Number NDC0005A VIN 1 SNS GND 2 VOUT VEN 3 Figure 3. 6-Lead WSON (LP38691SD-X.
PAGE 3
LP38691, LP38693 www.ti.com SNVS321K – JANUARY 2005 – REVISED APRIL 2013 ABSOLUTE MAXIMUM RATINGS (1) (2) −65°C to +150°C Storage Temperature Range Lead Temp. (Soldering, 5 seconds) 260°C ESD Rating (3) 2 kV Power Dissipation (4) Internally Limited V(max) All pins (with respect to GND) -0.3V to 12V IOUT (5) Internally Limited Junction Temperature −40°C to +150°C (1) (2) (3) (4) (5) Absolute maximum ratings indicate limits beyond which damage to the component may occur.
PAGE 4
LP38691, LP38693 SNVS321K – JANUARY 2005 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range. Unless otherwise specified: VIN = VOUT + 1V, CIN = COUT = 10 µF, ILOAD = 10mA. Min/Max limits are specified through testing, statistical correlation, or design. Symbol Parameter Conditions Min Typ (1) Max -2.0 2.0 -4.0 4.0 Units VO Output Voltage Tolerance 100 µA < IL < 0.
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LP38691, LP38693 www.ti.com SNVS321K – JANUARY 2005 – REVISED APRIL 2013 BLOCK DIAGRAMS VIN P-FET N/C + ENABLE LOGIC P-FET MOSFET DRIVER FOLDBACK CURRENT LIMITING VOUT SNS THERMAL SHUTDOWN 1.25V REFERENCE R1 R2 GND Figure 5. LP38691 Functional Diagram (WSON) VIN P-FET + ENABLE LOGIC P-FET MOSFET DRIVER FOLDBACK CURRENT LIMITING THERMAL SHUTDOWN VOUT 1.25V REFERENCE R1 R2 GND Figure 6.
PAGE 6
LP38691, LP38693 SNVS321K – JANUARY 2005 – REVISED APRIL 2013 www.ti.com VIN P-FET VEN ENABLE LOGIC + P-FET MOSFET DRIVER FOLDBACK CURRENT LIMITING VOUT SNS THERMAL SHUTDOWN 1.25V REFERENCE R1 R2 GND Figure 7. LP38693 Functional Diagram (WSON) VIN P-FET VEN ENABLE LOGIC + P-FET MOSFET DRIVER FOLDBACK CURRENT LIMITING THERMAL SHUTDOWN VOUT 1.25V REFERENCE R1 R2 GND Figure 8.
PAGE 7
LP38691, LP38693 www.ti.com SNVS321K – JANUARY 2005 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise specified: TJ = 25°C, CIN = COUT = 10 µF, Enable pin is tied to VIN (LP38693 only), VOUT = 1.8V, VIN = VOUT +1V, IL = 10mA. Noise vs Frequency Noise vs Frequency Figure 9. Figure 10. Noise vs Frequency Ripple Rejection 60 RIPPLE REJECTION (dB) 50 40 30 COUT = 10 PF 20 VIN(DC) = 5.3V VIN(AC) = 1V(p-p) 10 VOUT = 3.3V 0 10 100 1k 10k 100k FREQUENCY (Hz) Figure 11.
PAGE 8
LP38691, LP38693 SNVS321K – JANUARY 2005 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: TJ = 25°C, CIN = COUT = 10 µF, Enable pin is tied to VIN (LP38693 only), VOUT = 1.8V, VIN = VOUT +1V, IL = 10mA. Line Transient Response Line Transient Response VOUT = 3.3V COUT = 100 PF 'VOUT (mV) 20 10 VOUT 0 -10 -20 4 VIN (V) 5 VIN 3 200 Ps/DIV 8 Figure 15. Figure 16. Line Transient Response Load Transient Response Figure 17. Figure 18.
PAGE 9
LP38691, LP38693 www.ti.com SNVS321K – JANUARY 2005 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: TJ = 25°C, CIN = COUT = 10 µF, Enable pin is tied to VIN (LP38693 only), VOUT = 1.8V, VIN = VOUT +1V, IL = 10mA. VOUT vs Temperature (3.3V) VOUT vs Temperature (2.5V) Figure 21. Figure 22. VOUT vs Temperature (1.8V) VOUT vs VIN (1.8V) Figure 23. Figure 24. VOUT vs VIN, Power-Up VOUT vs VEN, ON (LP38693 Only) Figure 25. Figure 26.
PAGE 10
LP38691, LP38693 SNVS321K – JANUARY 2005 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: TJ = 25°C, CIN = COUT = 10 µF, Enable pin is tied to VIN (LP38693 only), VOUT = 1.8V, VIN = VOUT +1V, IL = 10mA. VOUT vs VEN, OFF (LP38693 Only) Enable Voltage vs Temperature Figure 27. Figure 28. Load Regulation vs Temperature Line Regulation vs Temperature Figure 29. Figure 30. MIN VIN vs IOUT Dropout Voltage vs IOUT 2.7 900 800 2.
PAGE 11
LP38691, LP38693 www.ti.com SNVS321K – JANUARY 2005 – REVISED APRIL 2013 APPLICATION HINTS EXTERNAL CAPACITORS Like any low-dropout regulator, external capacitors are required to assure stability. These capacitors must be correctly selected for proper performance. INPUT CAPACITOR: An input capacitor of at least 1µF is required (ceramic recommended). The capacitor must be located not more than one centimeter from the input pin and returned to a clean analog ground.
PAGE 12
LP38691, LP38693 SNVS321K – JANUARY 2005 – REVISED APRIL 2013 www.ti.com TANTALUM Solid Tantalum capacitors have good temperature stability: a high quality Tantalum will typically show a capacitance value that varies less than 10-15% across the full temperature range of -40°C to +125°C. ESR will vary only about 2X going from the high to low temperature limits. REVERSE VOLTAGE A reverse voltage condition will exist when the voltage at the output pin is higher than the voltage at the input pin.
PAGE 13
LP38691, LP38693 www.ti.com SNVS321K – JANUARY 2005 – REVISED APRIL 2013 The DAP (exposed pad) on the bottom of the WSON package is connected to the die substrate with a conductive die attach adhesive. The DAP has no direct electrical (wire) connection to any of the pins. There is a parasitic PN junction between the die substrate and the device ground. As such, it is strongly recommend that the DAP be connected directly to the ground at device lead 2 (i.e. GND).
PAGE 14
LP38691, LP38693 SNVS321K – JANUARY 2005 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision J (April 2013) to Revision K • 14 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
PAGE 15
PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LP38691DT-1.8 NRND TO-252 NDP 3 75 TBD Call TI Call TI -40 to 125 LP38691 DT-1.8 LP38691DT-1.8/NOPB ACTIVE TO-252 NDP 3 75 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 LP38691 DT-1.8 LP38691DT-2.
PAGE 16
PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 1-Nov-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LP38691QSD-3.3/NOPB ACTIVE WSON NGG 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L258B LP38691QSD-5.0/NOPB ACTIVE WSON NGG 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L259B LP38691QSDX-1.
PAGE 17
PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 1-Nov-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LP38693MP-3.3/NOPB ACTIVE SOT-223 NDC 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LJYB LP38693MP-5.0/NOPB ACTIVE SOT-223 NDC 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LJZB LP38693MPX-1.
PAGE 18
PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 1-Nov-2013 Status (1) LP38693SD-3.3/NOPB Package Type Package Pins Package Drawing Qty ACTIVE WSON NGG 6 1000 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L130B (4/5) LP38693SD-5.0 NRND WSON NGG 6 1000 TBD Call TI Call TI -40 to 125 L131B LP38693SD-5.
PAGE 19
PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
PAGE 20
PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LP38691DTX-1.8/NOPB TO-252 NDP 3 2500 330.0 16.4 6.9 10.5 2.7 8.0 16.0 Q2 LP38691DTX-2.5/NOPB TO-252 NDP 3 2500 330.0 16.4 6.9 10.5 2.7 8.0 16.0 Q2 LP38691DTX-3.3 TO-252 NDP 3 2500 330.0 16.4 6.9 10.5 2.7 8.0 16.
PAGE 21
PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LP38691SDX-1.8/NOPB WSON NGG 6 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 LP38691SDX-2.5/NOPB WSON NGG 6 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 LP38691SDX-3.3/NOPB WSON NGG 6 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 LP38691SDX-5.0/NOPB WSON NGG 6 4500 330.0 12.4 3.3 3.
PAGE 22
PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP38691DTX-1.8/NOPB TO-252 NDP 3 2500 367.0 367.0 38.0 LP38691DTX-2.5/NOPB TO-252 NDP 3 2500 367.0 367.0 38.0 LP38691DTX-3.3 TO-252 NDP 3 2500 367.0 367.0 35.0 LP38691DTX-3.3/NOPB TO-252 NDP 3 2500 367.0 367.0 38.0 LP38691DTX-5.0/NOPB TO-252 NDP 3 2500 367.0 367.0 38.0 LP38691QSD-1.
PAGE 23
PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP38691SDX-3.3/NOPB WSON NGG 6 4500 367.0 367.0 35.0 LP38691SDX-5.0/NOPB WSON NGG 6 4500 367.0 367.0 35.0 LP38693MP-1.8 SOT-223 NDC 5 1000 367.0 367.0 35.0 LP38693MP-1.8/NOPB SOT-223 NDC 5 1000 367.0 367.0 35.0 LP38693MP-2.5/NOPB SOT-223 NDC 5 1000 367.0 367.0 35.0 LP38693MP-3.3 SOT-223 NDC 5 1000 367.0 367.0 35.
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MECHANICAL DATA NDP0003B TD03B (Rev F) www.ti.
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MECHANICAL DATA NDC0005A www.ti.
PAGE 26
MECHANICAL DATA NGG0006A SDE06A (Rev A) www.ti.
PAGE 27
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.