Datasheet

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LP38692

OUT

SNS

GND

1 PF *

OUT

LP38690

OUT

SNS

GND

1 PF *

OUT

LP38690, LP38692

www.ti.com

SNVS322J –DECEMBER 2004–REVISED APRIL 2013

LP38690

LP38692 1A Low Dropout CMOS Linear Regulators

Stable with Ceramic Output Capacitors

Check for Samples: LP38690, LP38692

FEATURES

DESCRIPTION

The LP38690/2 low dropout CMOS linear regulators

• 2.5% Output Accuracy (25°C)

provide tight output tolerance (2.5% typical),

• Low Dropout Voltage: 450mV @ 1A (typ, 5V

extremely low dropout voltage (450mV @ 1A load

out)

current, V

OUT

= 5V), and excellent AC performance

• Wide Input Voltage Range (2.7V to 10V)

utilizing ultra low ESR ceramic output capacitors.

• Precision (Trimmed) Bandgap Reference

The low thermal resistance of the WSON, SOT-223

and PFM packages allow the full operating current to

• Ensured Specs for -40°C to +125°C

be used even in high ambient temperature

• 1µA Off-State Quiescent Current

environments.

• Thermal Overload Protection

The use of a PMOS power transistor means that no

• Foldback Current Limiting

DC base drive current is required to bias it allowing

• PFM, SOT-223 and 6-Lead WSON Packages

ground pin current to remain below 100 µA

regardless of load current, input voltage, or operating

• Enable Pin (LP38692)

temperature.

APPLICATIONS

Dropout Voltage: 450 mV (typ) @ 1A (typ. 5V out).

• Hard Disk Drives

Ground Pin Current: 55 µA (typ) at full load.

• Notebook Computers

Precision Output Voltage: 2.5% (25°C) accuracy.

• Battery Powered Devices

• Portable Instrumentation

Typical Application Circuits

* Minimum value required for stability.

**WSON package devices only.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (26 pages)

PAGE 1
LP38690, LP38692 www.ti.com SNVS322J – DECEMBER 2004 – REVISED APRIL 2013 LP38690 LP38692 1A Low Dropout CMOS Linear Regulators Stable with Ceramic Output Capacitors Check for Samples: LP38690, LP38692 FEATURES DESCRIPTION • • The LP38690/2 low dropout CMOS linear regulators provide tight output tolerance (2.5% typical), extremely low dropout voltage (450mV @ 1A load current, VOUT = 5V), and excellent AC performance utilizing ultra low ESR ceramic output capacitors. 1 2 • • • • • • • • 2.
PAGE 2
LP38690, LP38692 SNVS322J – DECEMBER 2004 – REVISED APRIL 2013 www.ti.com Connection Diagram VEN 1 N/C 2 5 GND VOUT 3 VIN 4 Figure 1. PFM (LP38690DT-X.X) – Top View See Package Number NDP0003B VIN 1 GND 2 N/C 3 Exposed Pad on Bottom (DAP) 6 VIN 5 4 Figure 2. SOT-223 (LP38692MP-X.X) – Top View See Package Number NDC0005A VIN 1 SNS GND 2 VOUT VEN 3 Figure 3. 6-Lead WSON (LP38690SD-X.
PAGE 3
LP38690, LP38692 www.ti.com SNVS322J – DECEMBER 2004 – REVISED APRIL 2013 ABSOLUTE MAXIMUM RATINGS (1) (2) −65°C to +150°C Storage Temperature Range Lead Temp. (Soldering, 5 seconds) 260°C ESD Rating (3) 2 kV Power Dissipation (4) Internally Limited V(max) All pins (with respect to GND) -0.3V to 12V IOUT (5) Internally Limited Junction Temperature −40°C to +150°C (1) (2) (3) (4) (5) Absolute maximum ratings indicate limits beyond which damage to the component may occur.
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LP38690, LP38692 SNVS322J – DECEMBER 2004 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range. Unless otherwise specified: VIN = VOUT + 1V, CIN = COUT = 10 µF, ILOAD = 10mA. Min/Max limits are specified through testing, statistical correlation, or design. Symbol IQ Parameter Conditions Min VIN ≤ 10V, IL =100 µA - 1A Quiescent Current VEN ≤ 0.
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LP38690, LP38692 www.ti.com SNVS322J – DECEMBER 2004 – REVISED APRIL 2013 VIN P-FET + ENABLE LOGIC P-FET MOSFET DRIVER FOLDBACK CURRENT LIMITING THERMAL SHUTDOWN VOUT 1.25V REFERENCE R1 R2 GND Figure 6. LP38690 Functional Diagram (PFM) VIN P-FET VEN + ENABLE LOGIC P-FET MOSFET DRIVER FOLDBACK CURRENT LIMITING VOUT SNS THERMAL SHUTDOWN 1.25V REFERENCE R1 R2 GND Figure 7.
PAGE 6
LP38690, LP38692 SNVS322J – DECEMBER 2004 – REVISED APRIL 2013 www.ti.com VIN P-FET VEN ENABLE LOGIC + P-FET MOSFET DRIVER FOLDBACK CURRENT LIMITING THERMAL SHUTDOWN VOUT 1.25V REFERENCE R1 R2 GND Figure 8.
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LP38690, LP38692 www.ti.com SNVS322J – DECEMBER 2004 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise specified: TJ = 25°C, CIN = COUT = 10 µF, Enable pin is tied to VIN (LP38692 only), VOUT = 1.8V, VIN = VOUT +1V, IL = 10mA. Noise vs Frequency Noise vs Frequency 1.0 1.2 COUT = 10 PF COUT = 1 PF Hz) 0.8 0.8 NOISE (PV/ NOISE/ (PV Hz) 1.0 0.6 0.4 0.6 0.4 0.2 0.2 0.0 0.0 10 100 1k 10k 100k 10 100 1k FREQUENCY (Hz) Figure 9.
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LP38690, LP38692 SNVS322J – DECEMBER 2004 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: TJ = 25°C, CIN = COUT = 10 µF, Enable pin is tied to VIN (LP38692 only), VOUT = 1.8V, VIN = VOUT +1V, IL = 10mA. Line Transient Response Line Transient Response VOUT = 3.3V VOUT 10 'VOUT (mV) 0 -10 COUT = 10 PF 50 VOUT 0 -50 -100 -20 VIN (V) VIN 4 4 3 3 200 Ps/DIV 100 Ps/DIV Figure 15. Figure 16.
PAGE 9
LP38690, LP38692 www.ti.com SNVS322J – DECEMBER 2004 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: TJ = 25°C, CIN = COUT = 10 µF, Enable pin is tied to VIN (LP38692 only), VOUT = 1.8V, VIN = VOUT +1V, IL = 10mA. Load Transient Response Load Transient Response 400 400 COUT = 1 PF 'VOUT (mV) 'VOUT (mV) COUT = 1 PF 200 VOUT 0 -200 -400 200 0 VOUT -200 -400 0.01 ILOAD (A) ILOAD ILOAD (A) 0.5 1 ILOAD 0.01 10 Ps/DIV 10 Ps/DIV Figure 21.
PAGE 10
LP38690, LP38692 SNVS322J – DECEMBER 2004 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: TJ = 25°C, CIN = COUT = 10 µF, Enable pin is tied to VIN (LP38692 only), VOUT = 1.8V, VIN = VOUT +1V, IL = 10mA. VOUT vs VIN (1.8V) VOUT vs VIN (Power-Up) Figure 27. Figure 28. VOUT vs VEN, ON (LP38692 Only) VOUT vs VEN, OFF (LP38692 Only) Figure 29. Figure 30. Dropout Voltage vs IOUT Dropout Voltage vs IOUT 1000 1600 900 125°C 1400 VOUT = 3.
PAGE 11
LP38690, LP38692 www.ti.com SNVS322J – DECEMBER 2004 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: TJ = 25°C, CIN = COUT = 10 µF, Enable pin is tied to VIN (LP38692 only), VOUT = 1.8V, VIN = VOUT +1V, IL = 10mA. Enable Voltage vs Temperature Load Regulation vs Temperature -1.0 2.3 VIN = 10V 2.1 -1.5 'VOUT/'IOUT (%/A) 1.9 VEN (V) 1.7 VIN = 6V 1.5 1.3 1.1 0.9 VIN = 4V -2.0 -2.5 -3.0 0.7 0.5 -50 -25 0 25 50 75 100 -3.
PAGE 12
LP38690, LP38692 SNVS322J – DECEMBER 2004 – REVISED APRIL 2013 www.ti.com APPLICATION HINTS EXTERNAL CAPACITORS Like any low-dropout regulator, external capacitors are required to assure stability. These capacitors must be correctly selected for proper performance. INPUT CAPACITOR: An input capacitor of at least 1µF is required (ceramic recommended). The capacitor must be located not more than one centimeter from the input pin and returned to a clean analog ground.
PAGE 13
LP38690, LP38692 www.ti.com SNVS322J – DECEMBER 2004 – REVISED APRIL 2013 TANTALUM Solid Tantalum capacitors have good temperature stability: a high quality Tantalum will typically show a capacitance value that varies less than 10-15% across the full temperature range of -40°C to +125°C. ESR will vary only about 2X going from the high to low temperature limits. REVERSE VOLTAGE A reverse voltage condition will exist when the voltage at the output pin is higher than the voltage at the input pin.
PAGE 14
LP38690, LP38692 SNVS322J – DECEMBER 2004 – REVISED APRIL 2013 www.ti.com The DAP (exposed pad) on the bottom of the WSON package is connected to the die substrate with a conductive die attach adhesive. The DAP has no direct electrical (wire) connection to any of the pins. There is a parasitic PN junction between the die substrate and the device ground. As such, it is strongly recommend that the DAP be connected directly to the ground at device lead 2 (i.e. GND).
PAGE 15
LP38690, LP38692 www.ti.com SNVS322J – DECEMBER 2004 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision I (April 2013) to Revision J • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
PAGE 16
PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LP38690DT-1.8/NOPB ACTIVE TO-252 NDP 3 75 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 LP38690DT-2.5 ACTIVE TO-252 NDP 3 75 TBD Call TI Call TI -40 to 125 LP38690DT-2.
PAGE 17
PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 1-Nov-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LP38690SD-3.3/NOPB ACTIVE WSON NGG 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L115B LP38690SD-5.0/NOPB ACTIVE WSON NGG 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L116B LP38690SDX-1.
PAGE 18
PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 1-Nov-2013 Status (1) LP38692SD-3.3/NOPB Package Type Package Pins Package Drawing Qty ACTIVE WSON NGG 6 1000 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L125B (4/5) LP38692SD-5.0 NRND WSON NGG 6 1000 TBD Call TI Call TI -40 to 125 L126B LP38692SD-5.
PAGE 19
PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
PAGE 20
PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LP38690DTX-1.8/NOPB TO-252 NDP 3 2500 330.0 16.4 6.9 10.5 2.7 8.0 16.0 Q2 LP38690DTX-2.5/NOPB TO-252 NDP 3 2500 330.0 16.4 6.9 10.5 2.7 8.0 16.0 Q2 LP38690DTX-3.3 TO-252 NDP 3 2500 330.0 16.4 6.9 10.5 2.7 8.0 16.
PAGE 21
PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 Device Package Package Pins Type Drawing SPQ LP38692MP-2.5/NOPB SOT-223 NDC 5 1000 330.0 16.4 LP38692MP-3.3 SOT-223 NDC 5 1000 330.0 16.4 LP38692MP-3.3/NOPB SOT-223 NDC 5 1000 330.0 LP38692MP-5.0 SOT-223 NDC 5 1000 330.0 LP38692MP-5.0/NOPB SOT-223 NDC 5 1000 LP38692MPX-1.8/NOPB SOT-223 NDC 5 LP38692MPX-2.5/NOPB SOT-223 NDC 5 LP38692MPX-3.3/NOPB SOT-223 NDC LP38692MPX-5.
PAGE 22
PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP38690DTX-1.8/NOPB TO-252 NDP 3 2500 367.0 367.0 38.0 LP38690DTX-2.5/NOPB TO-252 NDP 3 2500 367.0 367.0 38.0 LP38690DTX-3.3 TO-252 NDP 3 2500 367.0 367.0 35.0 LP38690DTX-3.3/NOPB TO-252 NDP 3 2500 367.0 367.0 38.0 LP38690DTX-5.0/NOPB TO-252 NDP 3 2500 367.0 367.0 38.0 LP38690SD-1.8 WSON NGG 6 1000 210.0 185.0 35.
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MECHANICAL DATA NDP0003B TD03B (Rev F) www.ti.
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MECHANICAL DATA NDC0005A www.ti.
PAGE 25
MECHANICAL DATA NGG0006A SDE06A (Rev A) www.ti.
PAGE 26
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.