Datasheet

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LP3875-ADJ

OUT

ADJ

GND

10 PF

OUT

10 PF

Tantalum

INPUT

OUTPUT

1.5A

R1*

R2*

OUT

= 1.216 x (1+

)

SDSD

LP3875-ADJ

www.ti.com

SNVS247D –SEPTEMBER 2003–REVISED APRIL 2013

LP3875-ADJ 1.5A Fast Ultra Low Dropout Linear Regulators

Check for Samples: LP3875-ADJ

FEATURES

DESCRIPTION

The LP3875-ADJ fast ultra low-dropout linear

• Ultra Low Dropout Voltage

regulators operate from a +2.5V to +7.0V input

• Low Ground Pin Current

supply. These ultra low dropout linear regulators

• Load Regulation of 0.06%

respond very quickly to step changes in load, which

makes them suitable for low voltage microprocessor

• 10nA Quiescent Current in Shutdown Mode

applications. The LP3875-ADJ is developed on a

• Specified Output Current of 1.5A DC

CMOS process which allows low quiescent current

• Available in DDPAK/TO-263, TO-220 and SOT-

operation independent of output load current. This

223 Packages

CMOS process also allows the LP3875-ADJ to

operate under extremely low dropout conditions.

• Minimum Output Capacitor Requirements

• Overtemperature/Overcurrent Protection

Dropout Voltage: Ultra low dropout voltage; typically

38mV at 150mA load current and 380mV at 1.5A load

• −40°C to +125°C Junction Temperature Range

current.

APPLICATIONS

Ground Pin Current: Typically 6mA at 1.5A load

current.

• Microprocessor Power Supplies

Shutdown Mode: Typically 10nA quiescent current

• GTL, GTL+, BTL, and SSTL Bus Terminators

when the shutdown pin is pulled low.

• Power Supplies for DSPs

Adjustable Output Voltage: The output voltage may

• SCSI Terminator

be programmed via two external resistors.

• Post Regulators

• High Efficiency Linear Regulators

• Battery Chargers

• Other Battery Powered Applications

TYPICAL APPLICATION CIRCUIT

*See Application Hints

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (20 pages)

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LP3875-ADJ www.ti.com SNVS247D – SEPTEMBER 2003 – REVISED APRIL 2013 LP3875-ADJ 1.5A Fast Ultra Low Dropout Linear Regulators Check for Samples: LP3875-ADJ FEATURES DESCRIPTION • • • • • • The LP3875-ADJ fast ultra low-dropout linear regulators operate from a +2.5V to +7.0V input supply. These ultra low dropout linear regulators respond very quickly to step changes in load, which makes them suitable for low voltage microprocessor applications.
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LP3875-ADJ SNVS247D – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. CONNECTION DIAGRAM Figure 1. TO-220-5 Package (Top View) Bent, Staggered Leads Figure 2. DDPAK/TO-263-5 Package (Top View) GND 5 1 2 3 4 SD VIN VOUT ADJ Figure 3. SOT-223-5 Package (Top View) Table 1.
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LP3875-ADJ www.ti.com SNVS247D – SEPTEMBER 2003 – REVISED APRIL 2013 BLOCK DIAGRAM Figure 4. LP3875-ADJ ABSOLUTE MAXIMUM RATINGS (1) If Military/Aerospace specified devices are required, contact the Texas Instruments Semiconductor Sales Office/ Distributors for availability and specifications. −65°C to +150°C Storage Temperature Range Lead Temperature (Soldering, 5 sec.) ESD Rating 260°C (2) Power Dissipation 2 kV (3) Internally Limited Input Supply Voltage (Survival) −0.3V to +7.
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LP3875-ADJ SNVS247D – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS — LP3875-ADJ Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range. Unless otherwise specified: VIN = VO(NOM) + 1V, IL = 10 mA, COUT = 10µF, VSD = 2V. Symbol Parameter Conditions Typ (1) VADJ Adjust Pin Voltage VOUT +1V ≤ VIN ≤ 7V 10 mA ≤ IL ≤ 1.5A 1.216 IADJ Adjust Pin Input Current VOUT +1V ≤ VIN≤ 7V 10 mA ≤ IL ≤ 1.
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LP3875-ADJ www.ti.com SNVS247D – SEPTEMBER 2003 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise specified: TJ = 25°C, COUT = 10µF, CIN = 10µF, S/D pin is tied to VIN, VOUT = 2.5V, VIN = VO(NOM) + 1V, IL = 10mA Ground Curren vs Output Voltage IL = 1.5A Dropout Voltage vs Output Load Current 6 500 12 400 o 5C C o 25 300 oC 200 - 40 100 5 GROUND PIN CURRENT (mA)_ DROPOUT VOLTAGE (mV) 600 4 3 2 1 0 0 0.5 0 1.8 1.5 1 2.3 2.8 3.3 3.8 4.3 4.
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LP3875-ADJ SNVS247D – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: TJ = 25°C, COUT = 10µF, CIN = 10µF, S/D pin is tied to VIN, VOUT = 2.5V, VIN = VO(NOM) + 1V, IL = 10mA Load Transient Response CIN = COUT = 10µF, OSCON Load Transient Response CIN = COUT = 100µF, OSCON VOUT 100mV/DIV MAGNITUDE MAGNITUDE VOUT 100mV/DIV ILOAD 1A/DIV ILOAD 1A/DIV TIME (50Ps/DIV) TIME (50Ps/DIV) Figure 11. Figure 12.
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LP3875-ADJ www.ti.com SNVS247D – SEPTEMBER 2003 – REVISED APRIL 2013 Application Hints SETTING THE OUTPUT VOLTAGE The output voltage is set using the resistors R1 and R2 (see TYPICAL APPLICATION CIRCUIT). The output is also dependent on the reference voltage (typically 1.216V) which is measured at the ADJ pin. The output voltage is given by the equation: VOUT = VADJ x ( 1 + R1 / R2) (1) This equation does not include errors due to the bias current flowing in the ADJ pin which is typically about 10 nA.
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LP3875-ADJ SNVS247D – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com SELECTING A CAPACITOR It is important to note that capacitance tolerance and variation with temperature must be taken into consideration when selecting a capacitor so that the minimum required amount of capacitance is provided over the full operating temperature range. In general, a good Tantalum capacitor will show very little capacitance variation with temperature, but a ceramic may not be as good (depending on dielectric type).
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LP3875-ADJ www.ti.com SNVS247D – SEPTEMBER 2003 – REVISED APRIL 2013 It should be noted that stability problems have been seen in applications where "vias" to an internal ground plane were used at the ground points of the IC and the input and output capacitors. This was caused by varying ground potentials at these nodes resulting from current flowing through the ground plane. Using a single point ground technique for the regulator and it's capacitors fixed the problem.
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LP3875-ADJ SNVS247D – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com SHORT-CIRCUIT PROTECTION The LP3875-ADJ is short circuit protected and in the event of a peak over-current condition, the short-circuit control loop will rapidly drive the output PMOS pass element off. Once the power pass element shuts down, the control loop will rapidly cycle the output on and off until the average power dissipation causes the thermal shutdown circuit to respond to servo the on/off cycling to a lower frequency.
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LP3875-ADJ www.ti.com SNVS247D – SEPTEMBER 2003 – REVISED APRIL 2013 In this equation, θCH is the thermal resistance from the case to the surface of the heat sink and θJC is the thermal resistance from the junction to the surface of the case. θJC is about 3°C/W for a TO-220 package. The value for θCH depends on method of attachment, insulator, etc. θCH varies between 1.5°C/W to 2.5°C/W. If the exact value is unknown, 2°C/W can be assumed.
PAGE 12
LP3875-ADJ SNVS247D – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com Figure 19. θJA vs Copper(1 Ounce) Area for SOT-223 Package The following figures show different layout scenarios for SOT-223 package. Figure 20. SCENARIO A, θJA = 148°C/W 12 Figure 21.
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LP3875-ADJ www.ti.com SNVS247D – SEPTEMBER 2003 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision C (April 2013) to Revision D • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 7.5 2.2 12.0 16.0 Q3 LP3875EMP-ADJ/NOPB SOT-223 NDC 5 1000 330.0 16.4 LP3875EMPX-ADJ/NOPB SOT-223 NDC 5 2000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP3875EMP-ADJ/NOPB SOT-223 NDC 5 1000 367.0 367.0 35.0 LP3875EMPX-ADJ/NOPB SOT-223 NDC 5 2000 367.0 367.0 35.0 LP3875ESX-ADJ/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.
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MECHANICAL DATA NDC0005A www.ti.
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MECHANICAL DATA KTT0005B TS5B (Rev D) BOTTOM SIDE OF PACKAGE www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.