Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - LDO voltage regulator Positivbe, adjustable SO 8 PowerPad

BIAS

GND

OUT

BIAS

10 PF Ceramic

OUT

10 PF

Ceramic

BIAS

1 PF

GND

LP38852-ADJ

ADJ

LP38852

www.ti.com

SNVS482E –JANUARY 2007–REVISED APRIL 2013

1.5A Fast-Response High-Accuracy Adjustable LDO Linear Regulator with Enable and

Soft-Start

Check for Samples: LP38852

FEATURES

DESCRIPTION

The LP38852-ADJ is a high current, fast response

• Adjustable V

OUT

Range of 0.80V to 1.8V

regulator which can maintain output voltage

• Wide V

BIAS

Supply Operating Range of 3.0V to

regulation with extremely low input to output voltage

5.5V

drop. Fabricated on a CMOS process, the device

• Stable with 10µF Ceramic Capacitors

operates from two input voltages: V

BIAS

provides

voltage to drive the gate of the N-MOS power

• Dropout Voltage of 130 mV (Typical) at 1.5A

transistor, while V

is the input voltage which

Load Current

supplies power to the load. The use of an external

• Precision Output Voltage across All Line and

bias rail allows the part to operate from ultra low V

Load Conditions:

voltages. Unlike bipolar regulators, the CMOS

architecture consumes extremely low quiescent

– ±1.5% V

ADJ

for T

= 25°C

current at any output load current. The use of an N-

– ±2.0% V

ADJ

for 0°C ≤ T

≤ +125°C

MOS power transistor results in wide bandwidth, yet

– ±3.0% V

ADJ

for -40°C ≤ T

≤ +125°C

minimum external capacitance is required to maintain

• Over-Temperature and Over-Current loop stability.

Protection

The fast transient response of this device makes it

• Available in 8 Lead SO PowerPAD, 7 Lead TO-

suitable for use in powering DSP, Microcontroller

220 and 7 Lead DDPAK Packages

Core voltages and Switch Mode Power Supply post

regulators. The part is available in the TO-220 and

• −40°C to +125°C Operating Junction

DDPAK 7-pin packages.

Temperature Range

Dropout Voltage: 130 mV (typical) at 1.5A load

APPLICATIONS

current.

• ASIC Power Supplies In:

Low Ground Pin Current: 10 mA (typical) at 1.5A

load current.

– Desktops, Notebooks, and Graphics Cards,

Servers

Soft-Start: Programmable Soft-Start time.

– Gaming Set Top Boxes, Printers and

Precision ADJ Voltage: ±1.5% for T

= 25°C, and

Copiers

±2.0% for 0°C ≤ T

≤ +125°C, across all line and load

• Server Core and I/O Supplies

conditions

• DSP and FPGA Power Supplies

• SMPS Post-Regulator

Typical Application Circuit

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (29 pages)

PAGE 1
LP38852 www.ti.com SNVS482E – JANUARY 2007 – REVISED APRIL 2013 1.5A Fast-Response High-Accuracy Adjustable LDO Linear Regulator with Enable and Soft-Start Check for Samples: LP38852 FEATURES DESCRIPTION • • The LP38852-ADJ is a high current, fast response regulator which can maintain output voltage regulation with extremely low input to output voltage drop.
PAGE 2
LP38852 SNVS482E – JANUARY 2007 – REVISED APRIL 2013 www.ti.com Connection Diagrams Top View SS EN IN GND ADJ OUT BIAS Figure 1. DDPAK-7 Package See Package Number KTW0007B 1 2 3 4 5 6 7 LP38852T-ADJ 1 2 3 4 5 6 7 LP38852S-ADJ SS EN IN GND ADJ OUT BIAS Top View TAB IS GND TAB IS GND Figure 2. TO-220-7 Package See Package Number NDZ0007B Top View ADJ 1 8 N/C OUT 2 7 IN BIAS 3 6 EN GND 4 5 SS DAP Connect to GND Figure 3.
PAGE 3
LP38852 www.ti.com SNVS482E – JANUARY 2007 – REVISED APRIL 2013 Absolute Maximum Ratings (1) (2) −65°C to +150°C Storage Temperature Range Lead Temperature Soldering, 5 seconds ESD Rating Human Body Model (3) Power Dissipation (4) 260°C ±2 kV Internally Limited VIN Supply Voltage (Survival) −0.3V to +6.0V VBIAS Supply Voltage (Survival) −0.3V to +6.0V VSS SoftStart Voltage (Survival) −0.3V to +6.0V −0.3V to +6.
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LP38852 SNVS482E – JANUARY 2007 – REVISED APRIL 2013 www.ti.com Electrical Characteristics Unless otherwise specified: VOUT = 0.80V, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, VEN = VBIAS, IOUT = 10 mA, CIN = COUT = 10 µF, CBIAS = 1 µF, CSS = open. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are ensured through test, design, or statistical correlation.
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LP38852 www.ti.com SNVS482E – JANUARY 2007 – REVISED APRIL 2013 Electrical Characteristics (continued) Unless otherwise specified: VOUT = 0.80V, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, VEN = VBIAS, IOUT = 10 mA, CIN = COUT = 10 µF, CBIAS = 1 µF, CSS = open. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are ensured through test, design, or statistical correlation.
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LP38852 SNVS482E – JANUARY 2007 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics Refer to the Typical Application Circuit. Unless otherwise specified: TJ = 25°C, R1 = 1.40 kΩ, R2 = 1.00 kΩ, CFF= 0.01 µF, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = 10 µF Ceramic, COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, CSS = Open. 6 VBIAS Ground Pin Current (IGND(BIAS)) vs VBIAS VBIAS Ground Pin Current (IGND(BIAS)) vs Temperature Figure 4. Figure 5.
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LP38852 www.ti.com SNVS482E – JANUARY 2007 – REVISED APRIL 2013 Typical Performance Characteristics (continued) Refer to the Typical Application Circuit. Unless otherwise specified: TJ = 25°C, R1 = 1.40 kΩ, R2 = 1.00 kΩ, CFF= 0.01 µF, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = 10 µF Ceramic, COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, CSS = Open. VOUT vs Temperature VOUT vs VIN Figure 10. Figure 11. UVLO Thresholds vs Temperature Soft-Start rSS Variation vs Temperature Figure 12.
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LP38852 SNVS482E – JANUARY 2007 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Refer to the Typical Application Circuit. Unless otherwise specified: TJ = 25°C, R1 = 1.40 kΩ, R2 = 1.00 kΩ, CFF= 0.01 µF, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = 10 µF Ceramic, COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, CSS = Open. 8 Enable Pull-Down Current (IEN) vs Temperature Enable Pull-Up Resistor (rEN) vs Temperature Figure 16. Figure 17.
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LP38852 www.ti.com SNVS482E – JANUARY 2007 – REVISED APRIL 2013 Typical Performance Characteristics (continued) Refer to the Typical Application Circuit. Unless otherwise specified: TJ = 25°C, R1 = 1.40 kΩ, R2 = 1.00 kΩ, CFF= 0.01 µF, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = 10 µF Ceramic, COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, CSS = Open. Load Transient Response, COUT = 10 µF Ceramic Load Transient Response, COUT = 10 µF Ceramic Figure 22. Figure 23.
PAGE 10
LP38852 SNVS482E – JANUARY 2007 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Refer to the Typical Application Circuit. Unless otherwise specified: TJ = 25°C, R1 = 1.40 kΩ, R2 = 1.00 kΩ, CFF= 0.01 µF, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = 10 µF Ceramic, COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, CSS = Open. VBIAS PSRR VIN PSRR Figure 28. Figure 29. Output Noise Figure 30.
PAGE 11
LP38852 www.ti.com SNVS482E – JANUARY 2007 – REVISED APRIL 2013 Block Diagram OUT IN LP38852-ADJ BIAS Under-Voltage Lock-Out Thermal Shut Down rEN ADJ EN Enable 1.2V rSS VREF SS ILIMIT GND 0.6V APPLICATION INFORMATION EXTERNAL CAPACITORS To assure regulator stability, input and output capacitors are required as shown in the Typical Application Circuit. Output Capacitor A minimum output capacitance of 10 µF, ceramic, is required for stability.
PAGE 12
LP38852 SNVS482E – JANUARY 2007 – REVISED APRIL 2013 www.ti.com Feed Forward Capacitor, CFF (Refer to the Typical Application Circuit) When using a ceramic capacitor for COUT, the typical ESR value will be too small to provide any meaningful positive phase compensation, FZ, to offset the internal negative phase shifts in the gain loop. FZ = (1 / (2 x π x COUT x ESR) ) (1) A capacitor placed across the gain resistor R1 will provide additional phase margin to improve load transient response of the device.
PAGE 13
LP38852 www.ti.com SNVS482E – JANUARY 2007 – REVISED APRIL 2013 Table 1 lists some suggested, best fit, standard ±1% resistor values for R1 and R2, and a standard ±10% capacitor values for CFF, for a range of VOUT values. Other values of R1, R2, and CFF are available that will give similar results. Table 1. VOUT R1 R2 CFF FZ 0.8V 1.07 kΩ 1.78 kΩ 12 nF 12.4 kHz 0.9V 1.50 kΩ 1.87 kΩ 8.2 nF 12.9 kHz 1.0V 1.00 kΩ 1.00 kΩ 12 nF 13.3 kHz 1.1V 1.65 kΩ 1.37 kΩ 8.2 nF 11.8 kHz 1.2V 1.
PAGE 14
LP38852 SNVS482E – JANUARY 2007 – REVISED APRIL 2013 www.ti.com REVERSE VOLTAGE A reverse voltage condition will exist when the voltage at the output pin is higher than the voltage at the input pin. Typically this will happen when VIN is abruptly taken low and COUT continues to hold a sufficient charge such that the input to output voltage becomes reversed. The NMOS pass element, by design, contains no body diode.
PAGE 15
LP38852 www.ti.com SNVS482E – JANUARY 2007 – REVISED APRIL 2013 Figure 32. Typical CSS vs COUT Values The CSS capacitor must be connected to a clean ground path back to the device ground pin. No components, other than CSS, should be connected to the SS pin, as there could be adverse effects to VOUT. If the Soft-Start function is not needed the SS pin should be left open, although some minimal capacitance value is always recommended.
PAGE 16
LP38852 SNVS482E – JANUARY 2007 – REVISED APRIL 2013 www.ti.com The maximum allowable junction temperature rise (ΔTJ) depends on the maximum anticipated ambient temperature (TA) for the application, and the maximum allowable operating junction temperature (TJ(MAX)).
PAGE 17
LP38852 www.ti.com SNVS482E – JANUARY 2007 – REVISED APRIL 2013 Figure 34. Maximum Power Dissipation vs Ambient Temperature for the DDPAK Package Figure 34 shows the maximum allowable power dissipation for DDPAK packages for different ambient temperatures, assuming θJA is 35°C/W and the maximum junction temperature is 125°C. Heat-Sinking the SO PowerPAD-8 Package The LP38852MR package has a θJA rating of 168°C/W, and a θJC rating of 11°C/W.
PAGE 18
LP38852 SNVS482E – JANUARY 2007 – REVISED APRIL 2013 www.ti.com Figure 36. Maximum Power Dissipation vs Ambient Temperature for the SO PowerPAD-8 Package Figure 36 shows the maximum allowable power dissipation for the SO PowerPAD-8 package for a range of ambient temperatures, assuming that θJA is 98°C/W and the maximum junction temperature is 125°C.
PAGE 19
LP38852 www.ti.com SNVS482E – JANUARY 2007 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision D (April 2013) to Revision E • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LP38852MRX-ADJ/NOPB SO Power PAD DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LP38852SX-ADJ/NOPB DDPAK/ TO-263 KTW 7 500 330.0 24.4 10.75 14.85 5.0 16.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP38852MRX-ADJ/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0 LP38852SX-ADJ/NOPB DDPAK/TO-263 KTW 7 500 367.0 367.0 45.
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MECHANICAL DATA NDZ0007B TA07B (Rev E) www.ti.
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MECHANICAL DATA DDA0008A MRA08A (Rev D) www.ti.
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MECHANICAL DATA KTW0007B TS7B (Rev E) BOTTOM SIDE OF PACKAGE www.ti.
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