Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - LDO voltage regulator Positivbe, adjustable SO 8 PowerPad

LP38853

www.ti.com

SNVS335D –DECEMBER 2006–REVISED APRIL 2013

LP38853 3A Fast-Response High-Accuracy Adjustable LDO Linear Regulator with Enable

and Soft-Start

Check for Samples: LP38853

FEATURES

DESCRIPTION

The LP38853-ADJ is a high current, fast response

• Adjustable V

OUT

Range of 0.80V to 1.8V

regulator which can maintain output voltage

• Wide V

BIAS

Supply Operating Range of 3.0V to

regulation with extremely low input to output voltage

5.5V

drop. Fabricated on a CMOS process, the device

• Stable with 10µF Ceramic Capacitors

operates from two input voltages: V

BIAS

provides

voltage to drive the gate of the N-MOS power

• Dropout Voltage of 240 mV (typical) at 3A Load

transistor, while V

is the input voltage which

Current

supplies power to the load. The use of an external

• Precision V

ADJ

Across All Line and Load

bias rail allows the part to operate from ultra low V

Conditions:

voltages. Unlike bipolar regulators, the CMOS

architecture consumes extremely low quiescent

– ±1.5% V

ADJ

for T

= 25°C

current at any output load current. The use of an N-

– ±2.0% V

ADJ

for 0°C ≤ T

≤ +125°C

MOS power transistor results in wide bandwidth, yet

– ±3.0% V

ADJ

for -40°C ≤ T

≤ +125°C

minimum external capacitance is required to maintain

• Over-Temperature and Over-Current loop stability.

Protection

The fast transient response of this device makes it

• Available in 8 Lead SO PowerPAD, 7 Lead PFM

suitable for use in powering DSP, Microcontroller

and 7 Lead DDPAK Packages

Core voltages and Switch Mode Power Supply post

regulators. The part is available in SO PowerPAD

• −40°C to +125°C Operating Junction

8–pin, PFM 7–pin, and DDPAK 7-pin packages.

Temperature Range

Dropout Voltage: 240 mV (typical) at 3A load

APPLICATIONS

current.

• ASIC Power Supplies in:

Low Ground Pin Current: 10 mA (typical) at 3A load

current.

– Desktops, Notebooks, and Graphics Cards,

Servers

Soft-Start: Programmable Soft-Start time.

– Gaming Set Top Boxes, Printers and

Precision ADJ Voltage: ±1.5% for T

= 25°C, and

Copiers

±2.0% for 0°C ≤ T

≤ +125°C, across all line and load

• Server Core and I/O Supplies

conditions

• DSP and FPGA Power Supplies

• SMPS Post-Regulator

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (28 pages)

PAGE 1
LP38853 www.ti.com SNVS335D – DECEMBER 2006 – REVISED APRIL 2013 LP38853 3A Fast-Response High-Accuracy Adjustable LDO Linear Regulator with Enable and Soft-Start Check for Samples: LP38853 FEATURES DESCRIPTION • • The LP38853-ADJ is a high current, fast response regulator which can maintain output voltage regulation with extremely low input to output voltage drop.
PAGE 2
LP38853 SNVS335D – DECEMBER 2006 – REVISED APRIL 2013 www.ti.com Typical Application Circuit LP38853-ADJ VIN IN VOUT OUT CIN 10 PF Ceramic VBIAS CFF R1 BIAS CBIAS 1 PF VEN COUT 10 PF Ceramic ADJ EN R2 SS GND CSS GND GND Connection Diagram TAB IS GND SS EN IN GND ADJ OUT BIAS Figure 1. DDPAK-7 – Top View See Package Number KTW0007B 1 2 3 4 5 6 7 LP38853T-ADJ 1 2 3 4 5 6 7 LP38853S-ADJ SS EN IN GND ADJ OUT BIAS TAB IS GND Figure 2.
PAGE 3
LP38853 www.ti.com SNVS335D – DECEMBER 2006 – REVISED APRIL 2013 PIN DESCRIPTIONS (continued) PFM-7 Pin # DDPAK-7 Pin # SO PowerPAD8 Pin # Pin Symbol - - DAP DAP Pin Description The SO PowerPAD DAP is a thermal connection only that is physically attached to the backside of the die, and used as a thermal heat-sink connection. See the Application Information section for details. These devices have limited built-in ESD protection.
PAGE 4
LP38853 SNVS335D – DECEMBER 2006 – REVISED APRIL 2013 www.ti.com Electrical Characteristics Unless otherwise specified: VOUT = 0.80V, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, VEN = VBIAS, IOUT = 10 mA, CIN = COUT = 10 µF, CBIAS = 1 µF, CSS = open. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation.
PAGE 5
LP38853 www.ti.com SNVS335D – DECEMBER 2006 – REVISED APRIL 2013 Electrical Characteristics (continued) Unless otherwise specified: VOUT = 0.80V, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, VEN = VBIAS, IOUT = 10 mA, CIN = COUT = 10 µF, CBIAS = 1 µF, CSS = open. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation.
PAGE 6
LP38853 SNVS335D – DECEMBER 2006 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics Refer to the Typical Application Circuit. Unless otherwise specified: TJ = 25°C, R1 = 1.40 kΩ, R2 = 1.00 kΩ, CFF= 0.01 µF, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = 10 µF Ceramic, COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, , CSS = Open. 6 VBIAS Ground Pin Current (IGND(BIAS)) vs VBIAS VBIAS Ground Pin Current (IGND(BIAS)) vs Temperature Figure 4. Figure 5.
PAGE 7
LP38853 www.ti.com SNVS335D – DECEMBER 2006 – REVISED APRIL 2013 Typical Performance Characteristics (continued) Refer to the Typical Application Circuit. Unless otherwise specified: TJ = 25°C, R1 = 1.40 kΩ, R2 = 1.00 kΩ, CFF= 0.01 µF, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = 10 µF Ceramic, COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, , CSS = Open. VOUT vs Temperature VOUT vs VIN Figure 10. Figure 11. UVLO Thresholds vs Temperature Soft-Start rSS Variation vs Temperature Figure 12.
PAGE 8
LP38853 SNVS335D – DECEMBER 2006 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Refer to the Typical Application Circuit. Unless otherwise specified: TJ = 25°C, R1 = 1.40 kΩ, R2 = 1.00 kΩ, CFF= 0.01 µF, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = 10 µF Ceramic, COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, , CSS = Open. 8 Enable Pull-Down Current (IEN) vs Temperature Enable Pull-Up Resistor (rEN) vs Temperature Figure 16. Figure 17.
PAGE 9
LP38853 www.ti.com SNVS335D – DECEMBER 2006 – REVISED APRIL 2013 Typical Performance Characteristics (continued) Refer to the Typical Application Circuit. Unless otherwise specified: TJ = 25°C, R1 = 1.40 kΩ, R2 = 1.00 kΩ, CFF= 0.01 µF, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = 10 µF Ceramic, COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, , CSS = Open. Load Transient Response, COUT = 10 µF Ceramic Load Transient Response, COUT = 10 µF Ceramic Figure 22. Figure 23.
PAGE 10
LP38853 SNVS335D – DECEMBER 2006 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Refer to the Typical Application Circuit. Unless otherwise specified: TJ = 25°C, R1 = 1.40 kΩ, R2 = 1.00 kΩ, CFF= 0.01 µF, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = 10 µF Ceramic, COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, , CSS = Open. VBIAS PSRR VIN PSRR Figure 28. Figure 29. Output Noise Figure 30.
PAGE 11
LP38853 www.ti.com SNVS335D – DECEMBER 2006 – REVISED APRIL 2013 Block Diagram OUT IN LP38853-ADJ BIAS Under-Voltage Lock-Out Thermal Shut Down rEN ADJ EN Enable 1.2V rSS SS VREF ILIMIT GND 0.5V APPLICATION INFORMATION EXTERNAL CAPACITORS To assure regulator stability, input and output capacitors are required as shown in the Typical Application Circuit. Output Capacitor A minimum output capacitance of 10 µF, ceramic, is required for stability.
PAGE 12
LP38853 SNVS335D – DECEMBER 2006 – REVISED APRIL 2013 www.ti.com Bias Capacitor The capacitor on the bias pin must be at least 1 µF, and can be any good quality capacitor (ceramic is recommended). Feed Forward Capacitor, CFF (Refer to theTypical Application Circuit) When using a ceramic capacitor for COUT, the typical ESR value will be too small to provide any meaningful positive phase compensation, FZ, to offset the internal negative phase shifts in the gain loop.
PAGE 13
LP38853 www.ti.com SNVS335D – DECEMBER 2006 – REVISED APRIL 2013 It is recommended that the values selected for R1 and R2 are such that the parallel value is less than 10 kΩ. This is to prevent internal parasitic capacitances on the ADJ pin from interfering with the FZ pole set by R1 and CFF. ( (R1 x R2) / (R1 + R2) ) ≤ 10 kΩ (6) Table 1 lists some suggested, best fit, standard ±1% resistor values for R1 and R2, and a standard ±10% capacitor values for CFF, for a range of VOUT values.
PAGE 14
LP38853 SNVS335D – DECEMBER 2006 – REVISED APRIL 2013 www.ti.com In any case, the output voltage cannot be ensured until both VIN and VBIAS are within the range of specified operating values. If used in a dual-supply system where the regulator output load is returned to a negative supply, the output pin must be diode clamped to ground. A Schottky diode is recommended for this diode clamp.
PAGE 15
LP38853 www.ti.com SNVS335D – DECEMBER 2006 – REVISED APRIL 2013 Figure 32. Typical CSS vs COUT Values The CSS capacitor must be connected to a clean ground path back to the device ground pin. No components, other than CSS, should be connected to the SS pin, as there could be adverse effects to VOUT. If the Soft-Start function is not needed the SS pin should be left open, although some minimal capacitance value is always recommended.
PAGE 16
LP38853 SNVS335D – DECEMBER 2006 – REVISED APRIL 2013 www.ti.com The total power dissipation is then: PD = PD(PASS) + PD(BIAS) + PD(IN) (11) The maximum allowable junction temperature rise (ΔTJ) depends on the maximum anticipated ambient temperature (TA) for the application, and the maximum allowable operating junction temperature (TJ(MAX)) .
PAGE 17
LP38853 www.ti.com SNVS335D – DECEMBER 2006 – REVISED APRIL 2013 MAXIMUM POWER DISSIPATION (W) 5 PFM Package 1 Sq Inch of 1 oz. Copper qJA = 35°C/W 4 3 TJ =125°C 2 TJ < 125°C 1 0 –50 –25 0 25 50 75 100 125 AMBIENT TEMPERATURE (°C) Figure 33. θJA vs Copper (1 Ounce) Area for the DDPAK package Figure 34.
PAGE 18
LP38853 SNVS335D – DECEMBER 2006 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision C (April 2013) to Revision D • 18 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
PAGE 19
PACKAGE OPTION ADDENDUM www.ti.
PAGE 20
PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line.
PAGE 21
PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LP38853MRX-ADJ/NOPB SO Power PAD DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LP38853SX-ADJ/NOPB DDPAK/ TO-263 KTW 7 500 330.0 24.4 10.75 14.85 5.0 16.0 24.
PAGE 22
PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP38853MRX-ADJ/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0 LP38853SX-ADJ/NOPB DDPAK/TO-263 KTW 7 500 367.0 367.0 45.
PAGE 23
MECHANICAL DATA NDZ0007B TA07B (Rev E) www.ti.
PAGE 24
PAGE 25
PAGE 26
MECHANICAL DATA DDA0008A MRA08A (Rev D) www.ti.
PAGE 27
MECHANICAL DATA KTW0007B TS7B (Rev E) BOTTOM SIDE OF PACKAGE www.ti.
PAGE 28
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.