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LP3892

www.ti.com

SNVS236D –SEPTEMBER 2003–REVISED APRIL 2013

LP3892 1.5A Fast-Response Ultra Low Dropout Linear Regulators

Check for Samples: LP3892

FEATURES

DESCRIPTION

The LP3892 is a high current, fast response regulator

• Ultra Low Dropout Voltage (140 mV at 1.5A

which can maintain output voltage regulation with

typ)

minimum input to output voltage drop. Fabricated on

• Low Ground Pin Current

a CMOS process, the device operates from two input

• Load Regulation of 0.04%/A

voltages: Vbias provides voltage to drive the gate of

the N-MOS power transistor, while Vin is the input

• 60 nA Typical Quiescent Current in Shutdown

voltage which supplies power to the load. The use of

• 1.5% Output Accuracy (25°C)

an external bias rail allows the part to operate from

• TO-220, DDPAK/TO-263 and SO PowerPAD-8

ultra low Vin voltages. Unlike bipolar regulators, the

Packages

CMOS architecture consumes extremely low

quiescent current at any output load current. The use

• Over Temperature/Over Current Protection

of an N-MOS power transistor results in wide

• −40°C to +125°C Junction Temperature Range

bandwidth, yet minimum external capacitance is

required to maintain loop stability.

APPLICATIONS

The fast transient response of these devices makes

• DSP Power Supplies

them suitable for use in powering DSP,

Microcontroller Core voltages and Switch Mode

• Server Core and I/O Supplies

Power Supply post regulators. The parts are available

• PC Add-in-Cards

in TO-220, DDPAK/TO-263 and SO PowerPAD-8

• Local Regulators in Set-Top Boxes

packages.

• Microcontroller Power Supplies

Dropout Voltage:140mV (typ) at 1.5A load current.

• High Efficiency Power Supplies

Ground Pin Current: 3 mA (typ) at full load.

• SMPS Post-Regulators

Shutdown Current: 60 nA (typ) when S/D pin is low.

Precision Output Voltage: 1.5% room temperature

accuracy.

TYPICAL APPLICATION CIRCUIT

At least 10 µF of input and output capacitance is required for stability.

*Tantalum capacitors are recommended. Aluminum electrolytic capacitors may be used for restricted temperature

range. See application hints.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (18 pages)

PAGE 1
LP3892 www.ti.com SNVS236D – SEPTEMBER 2003 – REVISED APRIL 2013 LP3892 1.5A Fast-Response Ultra Low Dropout Linear Regulators Check for Samples: LP3892 FEATURES DESCRIPTION • The LP3892 is a high current, fast response regulator which can maintain output voltage regulation with minimum input to output voltage drop.
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LP3892 SNVS236D – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. CONNECTION DIAGRAM Figure 1. TO-220, Top View Figure 2. DDPAK/TO-263, Top View VOUT 1 VOUT 2 VBIAS 3 GND 4 GND 8 N/C 7 VIN 6 S/D 5 GND Figure 3.
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LP3892 www.ti.com SNVS236D – SEPTEMBER 2003 – REVISED APRIL 2013 ABSOLUTE MAXIMUM RATINGS (1) VALUE / UNITS −65°C to +150°C Storage Temperature Range Lead Temp. (Soldering, 5 seconds) 260°C ESD Rating Human Body Model Machine Model (3) 2 kV 200V Power Dissipation (2) (4) Internally Limited VIN Supply Voltage (Survival) −0.3V to +6V VBIAS Supply Voltage (Survival) −0.3V to +7V −0.3V to +7V Shutdown Input Voltage (Survival) IOUT (Survival) Internally Limited −0.
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LP3892 SNVS236D – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range. Unless otherwise specified: VIN = VO(NOM) + 1V, VBIAS = 4.5V, IL = 10 mA, CIN = COUT = 10µF, VS/D = VBIAS. Symbol VO Parameter Conditions 10 mA ≤ IL≤ 1.5A, VO(NOM) + 1V ≤ VIN ≤ 5.5V, 4.
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LP3892 www.ti.com SNVS236D – SEPTEMBER 2003 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise specified: TJ = 25°C, COUT = 10 µF, Cin = 10 µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V. IGND vs VSD VOUT vs Temperature Figure 4. Figure 5. DC Load Regulation Line Regulation vs VIN Figure 6. Figure 7. Line Regulation vs VBIAS IBIAS vs IL 1.60 VBIAS = 5V VIN = 2.3V IBIAS (mA) 1.40 125oC 1.20 25oC 1.00 -40oC 0.80 0.60 0 0.5 1.0 1.5 LOAD CURRENT (A) Figure 8.
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LP3892 SNVS236D – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: TJ = 25°C, COUT = 10 µF, Cin = 10 µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V. 6 IGND vs VSD Noise Measurement Figure 10. Figure 11. VOUTStartup Waveform VOUTStartup Waveform Figure 12. Figure 13. Line Regulation vs VBIAS Line Regulation vs VBIAS Figure 14. Figure 15.
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LP3892 www.ti.com SNVS236D – SEPTEMBER 2003 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: TJ = 25°C, COUT = 10 µF, Cin = 10 µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V. VIN PSRR VIN PSRR Figure 16. Figure 17. VBIAS PSRR Figure 18.
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LP3892 SNVS236D – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com Application Hints EXTERNAL CAPACITORS To assure regulator stability, input and output capacitors are required as shown in the Typical Application Circuit. OUTPUT CAPACITOR At least 10µF of output capacitance is required for stability (the amount of capacitance can be increased without limit). The output capacitor must be located less than 1 cm from the output pin of the IC and returned to a clean analog ground.
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LP3892 www.ti.com SNVS236D – SEPTEMBER 2003 – REVISED APRIL 2013 SHUTDOWN OPERATION Pulling down the shutdown (S/D) pin will turn-off the regulator. Pin S/D must be actively terminated through a pull-up resistor (10 kΩ to 100 kΩ) for a proper operation. If this pin is driven from a source that actively pulls high and low (such as a CMOS rail to rail comparator), the pull-up resistor is not required. This pin must be tied to Vin if not used.
PAGE 10
LP3892 SNVS236D – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com As shown in the graph below, increasing the copper area beyond 1 square inch produces very little improvement. The minimum value for θJA for the DDPAK/TO-263 package mounted to a PCB is 32°C/W. Figure 22 shows the maximum allowable power dissipation for DDPAK/TO-263 packages for different ambient temperatures, assuming θJA is 35°C/W and the maximum junction temperature is 125°C. Figure 21.
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LP3892 www.ti.com SNVS236D – SEPTEMBER 2003 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision C (April 2013) to Revision D • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LP3892EMR-1.2/NOPB ACTIVE SO PowerPAD DDA 8 95 Green (RoHS & no Sb/Br) SN | CU SN Level-3-260C-168 HR -40 to 125 3892E MR1.2 LP3892EMR-1.5/NOPB ACTIVE SO PowerPAD DDA 8 95 Green (RoHS & no Sb/Br) SN | CU SN Level-3-260C-168 HR -40 to 125 3892E MR1.
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PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LP3892EMRX-1.2/NOPB SO Power PAD DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LP3892EMRX-1.5/NOPB SO Power PAD DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LP3892ESX-1.2/NOPB DDPAK/ TO-263 KTT 5 500 330.0 24.4 10.75 14.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP3892EMRX-1.2/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0 LP3892EMRX-1.5/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0 LP3892ESX-1.2/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 LP3892ESX-1.5/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.
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MECHANICAL DATA DDA0008B MRA08B (Rev B) www.ti.
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MECHANICAL DATA KTT0005B TS5B (Rev D) BOTTOM SIDE OF PACKAGE www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.