# $ # $ # $ $ SBAS317E − APRIL 2004 − REVISED MAY 2006 ! " FEATURES ANALOG FEATURES D MSC1200 and MSC1201: D D D D D D D D D D D D − 24 Bits No Missing Codes − 22 Bits Effective Resolution At 10Hz − Low Noise: 75nV MSC1202: − 16 Bits No Missing Codes − 16 Bits Effective Resolution At 200Hz − Noise: 600nV PGA From 1 to 128 Precision On-Chip Voltage Reference 8 Diff/Single-E
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# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 ELECTRICAL CHARACTERISTICS: AVDD = 5V All specifications from TMIN to TMAX, DVDD = +2.7V to +5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, ADC Bipolar Mode, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise noted. MSC120x PARAMETER CONDITION MIN TYP MAX UNITS Analog Input (AIN0-AIN5, AINCOM) Analog Input Range Buffer OFF AGND − 0.1 AVDD + 0.1 V Buffer ON AGND + 50mV AVDD − 1.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 ELECTRICAL CHARACTERISTICS: AVDD = 5V (continued) All specifications from TMIN to TMAX, DVDD = +2.7V to +5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, ADC Bipolar Mode, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise noted.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 ELECTRICAL CHARACTERISTICS: AVDD = 3V All specifications from TMIN to TMAX, DVDD = +2.7V to +5.25V, VREF ≡ (REF IN+) − (REF IN−) = +1.25V, unless otherwise noted. fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, ADC Bipolar Mode, and MSC120x PARAMETER CONDITIONS MIN TYP MAX UNITS Analog Input (AIN0-AIN5, AINCOM) Analog Input Range Buffer OFF AGND − 0.1 AVDD + 0.1 V Buffer ON AGND + 50mV AVDD − 1.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 ELECTRICAL CHARACTERISTICS: AVDD = 3V (continued) All specifications from TMIN to TMAX, DVDD = +2.7V to +5.25V, VREF ≡ (REF IN+) − (REF IN−) = +1.25V, unless otherwise noted. fMOD = 15.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 DIGITAL CHARACTERISTICS: DVDD = 2.7V to 5.25V All specifications from TMIN to TMAX, FMCON = 10h, all digital outputs high, and PDCON = 00h (all peripherals ON) or PDCON = FFh (all peripherals OFF), unless otherwise specified. MSC120x PARAMETER CONDITIONS MIN TYP MAX 2.7 3.3 3.6 UNITS Digital Power-Supply Requirements DVDD Digital Power-Supply Current 0.7 mA Normal Mode, fOSC = 1MHz, All Peripherals OFF 0.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 AC ELECTRICAL CHARACTERISTICS(1): DVDD = 2.7V to 5.25V MSC120x PARAMETER MIN CONDITION PHASE LOCK LOOP (PLL) Input Frequency Range PLL LF Mode PLL HF Mode PLL Lock Time TYP External Crystal/Clock Frequency (fOSC) PLLDIV = 449 (default) PLLDIV = 899 (must be set by user), DVDD = 5V Within 1% INTERNAL OSCILLATOR (IO) IO LF Mode IO HF Mode IO Settling Time MAX UNITS 2 kHz MHz MHz ms 1 MHz MHz ms 32.768 14.8 29.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 P3.6/SCK/SCL/CLKS PIN CONFIGURATIONS P1.7/INT5 P3.0/RxD0 P3.1/TxD0 P3.2/INT0 P3.4/T0 P3.3/INT1 TQFP P3.5/T1 P3.7 DVDD NC(1) DGND Top View 48 47 46 45 44 43 42 41 40 39 38 37 NC(1) 1 36 DVDD XIN 2 35 DVDD 3 34 DGND DGND 4 33 DGND XOUT RST 5 32 P1.6/INT4 NC(1) 6 NC(1) 7 NC(1) 31 P1.5/INT3 MSC1200 30 P1.4/INT2/SS 8 29 P1.3/DIN AVDD 9 28 P1.2/DOUT AGND 10 27 P1.1 AGND 11 26 P1.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 PIN ASSIGNMENTS MSC1200 PIN # MSC1201/1202 PIN # NC 1, 6, 7, 8, 16, 25, 47 5 No Connection. Leave unconnected. XIN 2 1 The crystal oscillator pin XIN supports parallel resonant AT-cut fundamental frequency crystals and ceramic resonators. XIN can also be an input if there is an external clock source instead of a crystal. XIN must not be left floating.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 TYPICAL CHARACTERISTICS: MSC1200 AND MSC1201 ONLY AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, ADC Bipolar Mode, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 TYPICAL CHARACTERISTICS: MSC1200 AND MSC1201 ONLY (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, ADC Bipolar Mode, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 TYPICAL CHARACTERISTICS: MSC1202 ONLY AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, ADC Bipolar Mode, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 TYPICAL CHARACTERISTICS: MSC1202 ONLY (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, ADC Bipolar Mode, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. FAST SETTLING FILTER EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO EFFECTIVE NUMBER OF BITS vs fMOD (set with ACLK) 20 20 19 fMOD = 203kHz 18 16 fMOD = 15.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 TYPICAL CHARACTERISTICS: ALL DEVICES AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, ADC Bipolar Mode, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. ADC INTEGRAL NONLINEARITY vs INPUT VOLTAGE ADC INTEGRAL NONLINEARITY vs INPUT VOLTAGE 15 15 ADC INL (ppm) 10 5 10 +25_ C −55_ C 0 −5 0 0.5 1.0 1.5 5 0 +85_ C −5 −10 +125_C +85_C −15 −2.5 −2.0 −1.5 −1.0 −0.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 TYPICAL CHARACTERISTICS: ALL DEVICES (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, ADC Bipolar Mode, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. ANALOG SUPPLY CURRENT vs ANALOG SUPPLY VOLTAGE 0.8 PGA = 128 DVDD = AVDD VREF = 1.25V 1.3 +125_ C 0.7 +85_ C AVDD = 5V, Buffer = ON 1.2 0.6 +25_ C IADC (µA) Analog Supply Current (mA) 1.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 TYPICAL CHARACTERISTICS: ALL DEVICES (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, ADC Bipolar Mode, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. DIGITAL SUPPLY CURRENT vs DIGITAL SUPPLY VOLTAGE 11 100 +125_ C 9 Normalized Gain (%) Digital Supply Current (mA) 101 PGA = 128 DVDD = AVDD VREF = 1.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 TYPICAL CHARACTERISTICS: ALL DEVICES (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, ADC Bipolar Mode, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. IDAC OUTPUT CURRENT AT TEMPERATURE vs ANALOG SUPPLY VOLTAGE IDAC OUTPUT CURRENT vs IDAC OUTPUT VOLTAGE 1020 1010 1.1 AVDD = 5V 0.9 0.7 AVDD = 3V 0.6 0.5 0.4 0.3 0.2 −55_C 1000 0.
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# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 ENHANCED 8051 CORE Single−Byte, Single−Cycle Instruction MSC120x Timing All instructions in the MSC120x families perform exactly the same functions as they would in a standard 8051. The effects on bits, flags, and registers are the same; however, the timing is different. The MSC120x families use an efficient 8051 core that results in an improved instruction execution speed of between 1.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 differently than the MSC1200 or MSC1201.) This gives the user the ability to add or subtract software functions and to migrate between family members. Thus, the MSC120x can become a standard device used across several application platforms. Furthermore, improvements were made to peripheral features that off-load processing from the core, and the user, to further improve efficiency.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 OVERVIEW The MSC120x ADC structure is shown in Figure 7. The figure lists the components that make up the ADC, along with the corresponding special function register (SFR) associated with each component.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 ADC INPUT MULTIPLEXER TEMPERATURE SENSOR The input multiplexer provides for any combination of differential inputs to be selected as the input channel, as shown in Figure 8. For example, if AIN0 is selected as the positive differential input channel, then any other channel can be selected as the negative differential input channel. With this method, it is possible to have up to six fully differential input channels.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Table 1. ENOB versus PGA (Bipolar Mode) ADC ANALOG INPUT When the buffer is not selected, the input impedance of the analog input changes with ACLK clock frequency (ACLK, SFR F6h) and gain (PGA). The relationship is: PGA SETTING 1 Impedance (W) + f SAMP @ CS ǒ Ǔ ǒ Ǔ 1MHz 7MW AIN Impedance (W) + @ ACLK Frequency PGA f CLK where ACLK frequency (f ACLK) + ACLK ) 1 and f MOD + f ACLK .
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 For system calibration, the appropriate signal must be applied to the inputs. It then computes an offset that will nullify offset in the system. The system gain calibration requires a positive full-scale differential input signal. It then computes a gain value to nullify gain errors in the system. Each of these calibrations will take seven tDATA periods to complete. (−3dB = 0.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 VOLTAGE REFERENCE RESET The MSC120x can use either an internal or external voltage reference. The voltage reference selection is controlled via ADC Control Register 0 (ADCON0, SFR DCh). The default power-up configuration for the voltage reference is 2.5V internal. The MSC120x can be reset from the following sources: The internal voltage reference can be selected as either 1.25V or 2.5V.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 POWER ON RESET The on-chip Power On Reset (POR) circuitry releases the device from reset when DVDD ≈ 2.0V. The power supply ramp rate does not affect the POR. If the power supply falls below 1.0V for longer than 200ms, the POR will execute. If the power supply falls below 1.0V for less than 200ms, unexpected operation may occur. If these conditions are not met, the POR will not execute.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 CLOCKS Internal Oscillator The MSC120x can operate in three separate clock modes: Internal Oscillator mode (IOM), External Clock mode (ECM), and Phase Lock Loop (PLL) mode. A block diagram is shown in Figure 13. The clock mode for the MSC120x is selected via the CLKSEL bits in HCR2. IO low-frequency (LF) mode is the default mode for the device.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 PLL XIN In PLL mode (HCR2, CLKSEL = 101 or HCR2, CLKSEL = 100), the CPU can execute from an external 32.768kHz crystal. This mode enables the use of a PLL circuit that synthesizes the selected clock frequencies (PLL LF mode or PLL HF mode). If an external clock is detected at startup, then the CPU begins execution in PLL mode after startup.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 D Toggle SCK by setting and clearing the port pin. D Memory Write Pulse (WR) that is idle high. SPI The MSC120x implement a basic SPI interface that includes the hardware for simple serial data transfers. Figure 17 shows a block diagram of the SPI. The peripheral supports master and slave modes, full duplex data transfers, both clock polarities, both clock phases, bit order, and slave select.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 SCK Cycle # 1 2 3 4 5 6 7 8 SCK (CPOL = 0) SCK (CPOL = 1) Sample Input MSB 6 5 4 3 2 1 LSB (CPHA = 0) Data Out Sample Input MSB 6 5 4 3 2 1 LSB (CPHA = 1) Data Out SS to Slave Slave CPHA = 1 Transfer in Progress 2 1) SS Asserted 1 2) First SCK Edge 3) CNTIF Set (dependent on CPHA bit) 4) SS Negated Slave CPHA = 0 Transfer in Progress 3 4 Figure 18.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 I2C The I/O pins needed for I2C transfer are serial clock (SCL) and serial data (SDA—implemented by connecting DIN and DOUT externally). The I2C transfer timing is shown in Figure 19. The MSC120x I2C supports: 1. Master or slave I2C operation (control in software) 2. Standard or fast modes of transfer 3. Clock stretching 4. General call When used in I2C mode, pins DIN (P1.3) and DOUT (P1.2) should be tied together externally.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Slave Operation Slave operation is supported, but address recognition, R/W determination, and ACK/NACK must be done under software control. The Disable Clock Stretch (DCS) bit can be set to disable clock stretching. When the DCS bit is set, the device will no longer stretch the clock and will not generate interrupts. This bit can be used to disable clock stretch interrupts when there is no address match.
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# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Figure 21 illustrates the Register Map. It is entirely separate from the Program and Data Memory areas discussed previously. A separate class of instructions is used to access the registers. There are 256 potential register locations. In practice, the MSC120x have 256 bytes of Scratchpad RAM and up to 128 SFRs. This is possible since the upper 128 Scratchpad RAM locations can only be accessed indirectly.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Stack Program Memory Another use of the Scratchpad area is for the programmer’s stack. This area is selected using the Stack Pointer (SP, SFR 81h). Whenever a call or interrupt is invoked, the return address is placed on the Stack. It also is available to the programmer for variables, etc., since the Stack can be moved and there is no fixed location within the RAM designated as Stack.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Serial Flash Programming Mode Serial Flash Programming mode (SFPM) is used to download Program and Data Memory into the onboard Flash Memory on the MSC120x. It is initiated by holding the P1.0/PROG pin low during the reset cycle, as shown in Figure 23. After the reset cycle, the host can communicate with the MSC120x through USART0. Refer to application note SBAA076 (www.ti.com) for serial programming commands and protocol.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Table 6. Interrupt Summary INTERRUPT ADDR NUM PRIORITY FLAG ENABLE PRIORITY CONTROL AVDD Low Voltage Detect 33h 6 High 0 ALVDIP (AIPOL.1)(1) EALV (AIE.1)(1) N/A Count (SPI/I2C) 33h 6 0 CNTIP (AIPOL.2)(1) ECNT (AIE.2)(1) N/A I2C Start/Stop 33h 6 0 I2CIP (AIPOL.3)(1) EI2C (AIE.3)(1) N/A INTERRUPT/EVENT MSECIP (AIPOL.4)(1) Milliseconds Timer 33h 6 0 ADC 33h 6 0 ADCIP (AIPOL.5)(1) EADC (AIE.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Hardware Configuration Register 0 (HCR0) CADDR 3Fh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 EPMA PML RSL EBR EWDR 1 DFSEL1 DFSEL0 NOTE: HCR0 is programmable only in SFPM, but can be read in UAM using the faddr_data_read Boot ROM routine. EPMA bit 7 Enable Program Memory Access (Security Bit). 0: After reset in programming modes, Flash Memory can only be accessed in UAM until a mass erase is done.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Hardware Configuration Register 1 (HCR1) CADDR 3Eh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DBSEL3 DBSEL2 DBSEL1 DBSEL0 1 DDB 1 1 NOTE: HCR1 is programmable only in SFPM, but can be read in UAM using the faddr_data_read Boot ROM routine. DBSEL3−0 Digital Supply Brownout Level Select. The values listed are nominal. The actual value will vary depending on device clock frequency and supply voltage.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Hardware Configuration Register 2 (HCR2) CADDR 3Dh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 0 0 CLKSEL2 CLKSEL1 CLKSEL0 NOTE: HCR2 is programmable only in SFPM, but can be read in UAM using the faddr_data_read Boot ROM routine. CLKSEL2−1 Clock Select.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Table 7.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Table 7. Special Function Registers (continued) ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET VALUE AEh P1DDRL P13H P13L P12H P12L P11H P11L P10H P10L 00h AFh P1DDRH P17H P17L P16H P16L P15H P15L P14H P14L 00h P3 P3.7 P3.6 SCK/SCL/CLKS P3.5 T1 P3.4 T0 P3.3 INT1 P3.2 INT0 P3.1 TXD0 P3.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Table 7.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Table 8.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Table 8. Special Function Register Cross Reference (continued) SFR ADDRESS FUNCTIONS CPU INTERRUPTS PORTS SERIAL COMM.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Stack Pointer (SP) SFR 81h SP.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0 07h Stack Pointer. The stack pointer identifies the location where the stack will begin. The stack pointer is incremented before every PUSH or CALL operation and decremented after each POP or RET/RETI. This register defaults to 07h after reset. Data Pointer Low 0 (DPL0) SFR 82h DPL0.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Power Control (PCON) SFR 87h 7 6 5 4 3 2 1 0 Reset Value SMOD 0 1 1 GF1 GF0 STOP IDLE 30h SMOD bit 7 Serial Port 0 Baud Rate Doubler Enable. The serial baud rate doubling function for Serial Port 0. 0: Serial Port 0 baud rate will be a standard baud rate. 1: Serial Port 0 baud rate will be double that defined by baud rate generation equation. GF1 bit 3 General-Purpose User Flag 1.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Timer Mode Control (TMOD) 7 SFR 89h 6 5 4 3 2 TIMER 1 GATE C/T 1 0 M1 M0 TIMER 0 M1 M0 GATE C/T GATE bit 7 Timer 1 Gate Control. This bit enables/disables the ability of Timer 1 to increment. 0: Timer 1 will clock when TR1 = 1, regardless of the state of pin INT1. 1: Timer 1 will clock only when TR1 = 1 and pin INT1 = 1. C/T bit 6 Timer 1 Counter/Timer Select. 0: Timer is incremented by internal clocks.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Timer 0 MSB (TH0) SFR 8Ch TH0.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value TH0.7 TH0.6 TH0.5 TH0.4 TH0.3 TH0.2 TH0.1 TH0.0 00h Timer 0 MSB. This register contains the most significant byte of Timer 0. Timer 1 MSB (TH1) SFR 8Dh TH1.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value TH1.7 TH1.6 TH1.5 TH1.4 TH1.3 TH1.2 TH1.1 TH1.0 00h Timer 1 MSB.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Port 1 (P1) SFR 90h 7 6 5 4 3 2 1 0 Reset Value P1.7 INT5 P1.6 INT4 P1.5 INT3 P1.4 INT2/SS P1.3 DIN P1.2 DOUT P1.1 P1.0 PROG FFh P1.7−0 bits 7−0 General-Purpose I/O Port 1. This register functions as a general-purpose I/O port. In addition, all the pins have an alternative function listed below. Each of the functions is controlled by several other SFRs.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Configuration Address (CADDR) (write-only) 7 6 5 4 3 2 1 0 SFR 93h CADDR bits 7−0 Reset Value 00h Configuration Address. This register supplies the address for reading bytes in the 128 bytes of Flash Configuration Memory. It is recommended that faddr_data_read be used when accessing Configuration memory.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Serial Data Buffer 0 (SBUF0) 7 6 5 4 3 2 1 0 SFR 99h SBUF0 bits 7−0 Reset Value 00h Serial Data Buffer 0. Data for Serial Port 0 is read from or written to this location. The serial transmit and receive buffers are separate registers, but both are addressed at this location.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 I2C Control (I2CCON) SFR 9Ah SBIT3−0 bits 7−4 7 6 5 4 3 2 1 0 Reset Value SBIT3 SBIT2 SBIT1 SBIT0 STOP START DCS CNTSEL 00h Serial Bit Count. Number of bits transferred (read-only). SBIT3:0 COUNT 0x00 0 0x01 1 0x03 2 0x02 3 0x06 4 0x07 5 0x05 6 0x04 7 0x0C 8 STOP bit 3 Stop-Bit Status.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Auxiliary Interrupt Poll (AIPOL) SFR A4h 7 6 5 4 3 2 1 0 Reset Value SECIP SUMIP ADCIP MSECIP I2CIP CNTIP ALVDIP 0 00h Interrupts are enabled by EICON.4 (SFR D8h). The other interrupts are controlled by the IE and EIE registers. SECIP bit 7 Second System Timer Interrupt Poll (before IRQ masking).
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Auxiliary Interrupt Enable (AIE) SFR A6h 7 6 5 4 3 2 1 0 Reset Value ESEC ESUM EADC EMSEC EI2C ECNT EALV 0 00h Interrupts are enabled by EICON.4 (SFR D8h). The other interrupts are controlled by the IE and EIE registers. ESEC bit 7 Enable Second System Timer Interrupt (lowest priority auxiliary interrupt). Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: Second Timer Interrupt mask.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Auxiliary Interrupt Status (AISTAT) SFR A7h 7 6 5 4 3 2 1 0 Reset Value SEC SUM ADC MSEC I2C CNT ALVD 0 00h SEC bit 7 Second System Timer Interrupt Status Flag (lowest priority AI). 0: SEC interrupt cleared or masked. 1: SEC Interrupt active (it is cleared by reading SECINT, SFR F9h). SUM bit 6 Summation Register Interrupt Status Flag. 0: SUM interrupt cleared or masked.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Interrupt Enable (IE) SFR A8h 7 6 5 4 3 2 1 0 Reset Value EA 0 0 ES0 ET1 EX1 ET0 EX0 00h EA bit 7 Global Interrupt Enable. This bit controls the global masking of all interrupts except those in AIE (SFR A6h). 0: Disable interrupt sources. This bit overrides individual interrupt mask settings for this register. 1: Enable all individual interrupt masks.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Port 1 Data Direction Low (P1DDRL) SFR AEh P1.3 bits 7−6 P1.2 bits 5−4 P1.1 bits 3−2 P1.0 bits 1−0 7 6 5 4 3 2 1 0 Reset Value P13H P13L P12H P12L P11H P11L P10H P10L 00h Port 1 bit 3 control. P13H P13L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 1 bit 2 control.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Port 1 Data Direction High (P1DDRH) SFR AFh P1.7 bits 7−6 P1.6 bits 5−4 P1.5 bits 3−2 P1.4 bits 1−0 60 7 6 5 4 3 2 1 0 Reset Value P17H P17L P16H P16L P15H P15L P14H P14L 00h Port 1 bit 7 control. P17H P17L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 1 bit 6 control.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Port 3 (P3) SFR B0h P3.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value P3.7 P3.6 SCK/SCL/CLKS P3.5 T1 P3.4 T0 P3.3 INT1 P3.2 INT0 P3.1 TXD0 P3.0 RXD0 FFh General-Purpose I/O Port 3. This register functions as a general-purpose I/O port. In addition, all the pins have an alternative function listed below. Each of the functions is controlled by several other SFRs.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Port 3 Data Direction Low (P3DDRL) SFR B3h P3.3 bits 7−6 P3.2 bits 5−4 P3.1 bits 3−2 P3.0 bits 1−0 62 7 6 5 4 3 2 1 0 Reset Value P33H P33L P32H P32L P31H P31L P30H P30L 00h Port 3 bit 3 control. P33H P33L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 3 bit 2 control.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Port 3 Data Direction High (P3DDRH) SFR B4h P3.7 bits 7−6 7 6 5 4 3 2 1 0 Reset Value P37H P37L P36H P36L P35H P35L P34H P34L 00h Port 3 bit 7 control. P37H P37L 0 0 Standard 8051 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input NOTE: Port 3.7 also controlled by EA and Memory Access Control HCR1.1. P3.6 bits 5−4 Port 3 bit 6 control.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 IDAC 7 SFR B5h IDAC bits 7−0 6 5 4 3 2 1 MSB 0 Reset Value LSB 00h Current DAC. IDACOUT = IDAC • 3.9µA (∼1mA full-scale). Setting (PDCON.PDIDAC) will shut down IDAC and float the IDAC pin. Interrupt Priority (IP) SFR B8h 7 6 5 4 3 2 1 0 Reset Value 1 0 0 PS0 PT1 PX1 PT0 PX0 80h PS0 bit 4 Serial Port 0 Interrupt. This bit controls the priority of the serial Port 0 interrupt.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 System Clock Divider (SYSCLK) SFR C7h 7 6 5 4 3 2 1 0 Reset Value 0 0 DIVMOD1 DIVMOD0 0 DIV2 DIV1 DIV0 00h NOTE: Changing the SYSCLK registers affects all internal clocks, including the ADC clock. DIVMOD1−0 Clock Divide Mode bits 5−4 Write: DIVMOD DIVIDE MODE 00 Normal mode (default, no divide).
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Program Status Word (PSW) SFR D0h 7 6 5 4 3 2 1 0 Reset Value CY AC F0 RS1 RS0 OV F1 P 00h CY bit 7 Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (during addition) or a borrow (during subtraction). Otherwise, it is cleared to ‘0’ by all arithmetic operations. AC bit 6 Auxiliary Carry Flag.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 ADC Offset Calibration Low Byte (OCL) 7 6 5 4 3 2 1 SFR D1h 0 Reset Value LSB 00h All MSC120x devices support 24-bit calibration values. OCL bits 7−0 ADC Offset Calibration Low Byte. This is the low byte of the 24-bit word that contains the ADC offset calibration. This value is written by the device after performing a calibration.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 ADC Gain Calibration High Byte (GCH) 7 SFR D6h 6 5 4 3 2 1 0 MSB Reset Value 5Fh All MSC120x devices support 24-bit calibration values. GCH bits 7−0 ADC Gain Calibration High Byte. This is the high byte of the 24-bit word that contains the ADC gain calibration. This value is written by the device after performing a calibration.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Enable Interrupt Control (EICON) SFR D8h 7 6 5 4 3 2 1 0 Reset Value 0 1 EAI AI WDTI 0 0 0 40h EAI bit 5 Enable Auxiliary Interrupt. The Auxiliary Interrupt accesses nine different interrupts which are masked and identified by SFR registers PAI (SFR A5h), AIE (SFR A6h), and AISTAT (SFR A7h). 0 = Auxiliary Interrupt disabled (default). 1 = Auxiliary Interrupt enabled. AI bit 4 Auxiliary Interrupt Flag.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 ADC Control 0 (ADCON0) SFR DCh 7 6 5 4 3 2 1 0 Reset Value — BOD EVREF VREFH EBUF PGA2 PGA1 PGA0 30h BOD bit 6 Burnout Detect. When enabled, this connects a positive current source to the positive channel and a negative current source to the negative channel. If the channel is open circuit, then the ADC results will be full-scale (buffer must be enabled). 0 = Burnout Current Sources Off (default).
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 ADC Control 1 (ADCON1) SFR DDh 7 6 5 4 3 2 1 0 Reset Value OF_UF POL SM1 SM0 — CAL2 CAL1 CAL0 00h OF_UF bit 6 Overflow/Underflow. If this bit is set, the data in the Summation register is invalid; either an overflow or underflow occurred. This bit is cleared by writing a ‘0’ to it. POL bit 6 Polarity. Polarity of the ADC result and Summation register. 0 = Bipolar. 1 = Unipolar.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 ADC Control 2 (ADCON2) SFR DEh DR7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 1Bh Decimation Ratio LSB (refer to ADCON3, SFR DFh). ADC Control 3 (ADCON3) SFR DFh 7 6 5 4 3 2 1 0 Reset Value — — — — — DR10 DR9 DR8 06h DR10−8 Decimation Ratio Most Significant 3 Bits.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Summation/Shifter Control (SSCON) SFR E1h 7 6 5 4 3 2 1 0 Reset Value SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 00h The Summation register is powered down when the ADC is powered down. If all zeroes are written to this register, the 32-bit SUMR3−0 registers will be cleared. The Summation registers will do sign-extend if Bipolar Mode is selected in ADCON1. SSCON1−0 Summation/Shift Count.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Summation 0 (SUMR0) 7 6 5 4 3 2 1 SFR E2h SUMR0 bits 7−0 0 Reset Value LSB 00h Summation 0. This is the least significant byte of the 32-bit summation register, or bits 0 to 7. Write: Will cause values in SUMR3−0 to be added to the summation register. Read: Will clear the Summation Interrupt. Summation 1 (SUMR1) 7 6 5 4 3 2 1 0 SFR E3h SUMR1 bits 7−0 Reset Value 00h Summation 1.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Low Voltage Detect Control (LVDCON) SFR E7h 7 6 5 4 3 2 1 0 Reset Value ALVDIS 0 0 0 ALVD3 ALVD2 ALVD1 ALVD0 8Fh ALVDIS bit 7 Analog Low Voltage Detect Disable. 0 = Enable Detection of Low Analog Supply Voltage (ALVD flag and interrupt are set when AVDD < ALVD threshold) 1 = Disable Detection of Low Analog Supply Voltage ALVD3−0 bits 7−4 Analog Low Voltage Detect. Sets ALVD threshold. 0000: 4.6V 0001: 4.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Hardware Product Code 0 (HWPC0) (read-only) SFR E9h 7 6 5 4 3 2 1 0 Reset Value 0 0 0 0 0 0 DEVICE MEMORY 0000_00xxb HWPC0.7−0 Hardware Product Code LSB. Read-only.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Flash Memory Control (FMCON) SFR EEh 7 6 5 4 3 2 1 0 Reset Value 0 PGERA 0 FRCM 0 BUSY SPM FPM 02h PGERA bit 6 Page Erase. Available in both user and program modes. 0 = Disable Page Erase Mode 1 = Enable Page Erase Mode (automatically set by page_erase Boot ROM routine) FRCM bit 4 Frequency Control Mode. 0 = Bypass (default) 1 = Use Delay Line. Recommended for saving power.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Power-Down Control (PDCON) SFR F1h 7 6 5 4 3 2 1 0 Reset Value PDICLK PDIDAC PDI2C 0 PDADC PDWDT PDST PDSPI 6Fh Turning peripheral modules off puts the MSC120x in the lowest power mode. PDICLK bit 7 Internal Clock Control. 0 = Internal Oscillator and PLL On (Internal Oscillator or PLL mode) 1 = Internal Oscillator and PLL Power Down (External Clock mode). Bit is not active on IOM or PLL mode.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 PSEN/ALE Select (PASEL) SFR F2h PSEN2−0 bits 7−3 7 6 5 4 3 2 1 0 Reset Value PSEN4 PSEN3 PSEN2 PSEN1 PSEN0 0 0 0 00h PSEN Mode Select. Defines the output on P3.6 in UAM or SFPM.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Phase Lock Loop High (PLLH) SFR F5h 7 6 5 4 3 2 1 0 Reset Value CLKSTAT2 CLKSTAT1 CLKSTAT0 PLLLOCK 0 0 PLL9 PLL8 xxh CLKSTAT2−0 Active Clock Status (read-only). Derived from HCR2 setting; refer to Table 3.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Extended Interrupt Priority (EIP) SFR F8h 7 6 5 4 3 2 1 0 Reset Value 1 1 1 PWDI PX5 PX4 PX3 PX2 E0h PWDI bit 4 Watchdog Interrupt Priority. This bit controls the priority of the watchdog interrupt. 0 = The watchdog interrupt is low priority. 1 = The watchdog interrupt is high priority. PX5 bit 3 External Interrupt 5 Priority. This bit controls the priority of external interrupt 5.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Milliseconds TImer Interrupt (MSINT) SFR FAh 7 6 5 4 3 2 1 0 Reset Value WRT MSINT6 MSINT5 MSINT4 MSINT3 MSINT2 MSINT1 MSINT0 7Fh The clock used for this timer is the 1ms clock, which results from dividing the system clock by the values in registers MSECH:MSECL. Reading this register is necessary for clearing the interrupt; however, AI in EICON (SFR D8h) must also be cleared. WRT bit 7 Write Control.
# $ # $ # $ $ www.ti.com SBAS317E − APRIL 2004 − REVISED MAY 2006 Watchdog Timer (WDTCON) SFR FFh 7 6 5 4 3 2 1 0 Reset Value EWDT DWDT RWDT WDCNT4 WDCNT3 WDCNT2 WDCNT1 WDCNT0 00h EWDT bit 7 Enable Watchdog (R/W). Write 1/Write 0 sequence sets the Watchdog Enable Counting bit. DWDT bit 6 Disable Watchdog (R/W). Write 1/Write 0 sequence clears the Watchdog Enable Counting bit. RWDT bit 5 Reset Watchdog (R/W). Write 1/Write 0 sequence restarts the Watchdog Counter.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device MSC1200Y2PFBT Package Package Pins Type Drawing TQFP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PFB 48 250 177.8 16.4 9.6 9.6 1.5 12.0 16.0 Q2 MSC1200Y3PFBT TQFP PFB 48 250 177.8 16.4 9.6 9.6 1.5 12.0 16.0 Q2 MSC1201Y3RHHT VQFN RHH 36 250 180.0 16.4 6.3 6.3 1.1 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSC1200Y2PFBT TQFP PFB 48 250 210.0 185.0 35.0 MSC1200Y3PFBT TQFP PFB 48 250 210.0 185.0 35.0 MSC1201Y3RHHT VQFN RHH 36 250 210.0 185.0 35.0 MSC1202Y2RHHT VQFN RHH 36 250 210.0 185.0 35.0 MSC1202Y3RHHR VQFN RHH 36 2500 367.0 367.0 38.0 MSC1202Y3RHHT VQFN RHH 36 250 210.0 185.0 35.
MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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