SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 !" # $ % FEATURES ANALOG FEATURES D 24 Bits No Missing Codes D 22 Bits Effective Resolution at 10Hz − Low Noise: 75nV D PGA From 1 to 128 D Precision On-Chip Voltage Reference D D D D D D D D − Accuracy: 0.2% − Drift: 5ppm/°C 8 Differential/Single-Ended Channels On-Chip Offset/Gain Calibration Offset Drift: 0.
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www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS: AVDD = 5V (continued) All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, AVDD = +5V, fMOD = 15.625kHz, PGA = 1, filter = Sinc3, Buffer ON, fDATA = 10Hz, Bipolar, fCLK = 8MHz, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise noted. For VDAC, VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF, unless otherwise noted.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS: AVDD = 5V (continued) All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, AVDD = +5V, fMOD = 15.625kHz, PGA = 1, filter = Sinc3, Buffer ON, fDATA = 10Hz, Bipolar, fCLK = 8MHz, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise noted. For VDAC, VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF, unless otherwise noted. MSC1211/12/13/14 PARAMETER CONDITIONS MIN TYP MAX 5 5.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS: AVDD = 3V (continued) All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, AVDD = +3V, fMOD = 15.625kHz, PGA = 1, filter = Sinc3, Buffer ON, fDATA = 10Hz, Bipolar, fCLK = 8MHz, and VREF ≡ (REF IN+) − (REF IN−) = +1.25V, unless otherwise noted. For VDAC, VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF, unless otherwise noted.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS: AVDD = 3V (continued) All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, AVDD = +3V, fMOD = 15.625kHz, PGA = 1, filter = Sinc3, Buffer ON, fDATA = 10Hz, Bipolar, fCLK = 8MHz, and VREF ≡ (REF IN+) − (REF IN−) = +1.25V, unless otherwise noted. For VDAC, VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF, unless otherwise noted.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 DIGITAL CHARACTERISTICS: DVDD = 2.7V to 5.25V All specifications from TMIN to TMAX, FMCON = 10h, all digital outputs high, PDCON = 00h (all peripherals ON) or PDCON = FFh (all peripherals OFF), PSEN and ALE enabled (all peripherals ON) or PSEN and ALE disabled (all peripherals OFF), unless otherwise specified. MSC1211/12/13/14 PARAMETER MIN CONDITIONS TYP MAX 3 3.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 AC ELECTRICAL CHARACTERISTICS(1)(2): DVDD = 2.7V to 5.25V 2.7V to 3.6V 4.75V to 5.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 EXPLANATION OF THE AC SYMBOLS Each Timing Symbol has five characters. The first character is always ’t’ (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ALE tWHLH PSEN tLLWL tWLWH WR tAVLL tLLAX tQ V W X tWHQX t DW PORT 0 A0−A7 from RI or DPL DATA OUT A0−A7 from PCL INSTR IN tAVWL PORT 2 P2.0−P2.7 or A8−A15 from DPH A8−A15 from PCH Figure 3. External Data Memory Write Cycle t HIGH VIH1 0.8V tr VIH1 0.8V VIH1 tLOW tf VIH1 0.8V 0.8V t OSC Figure 4.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 RESET AND POWER-ON TIMING tRW RST tRRD tRFD tRRD tRFD PSEN ALE tRS tRH EA NOTE: PSEN and ALE are internally pulled up with ~9kΩduring RST high. Figure 5. Reset Timing, User Application Mode tRW RST tRFD tRRD PSEN tRS tRRD tRH ALE NOTE: PSEN and ALE are internally pulled up with ~9kΩduring RST high. Figure 6.
www.ti.com P0.3/AD3 P0.4/AD4 P0.5/AD5 58 P0.2/AD2 59 P0.1/AD1 P1.2/RxD1 60 P0.0/AD0 P1.3/TxD1 61 P1.0/T2 P1.4/INT2/SS 62 P1.1/T2EX P1.5/INT3/MOSI 63 DGND P1.6/INT4/MISO/SDA(1) 64 DVDD P1.7/INT5/SCK/SCL(1) SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 57 56 55 54 53 52 51 50 49 XOUT 1 48 EA XIN 2 47 P0.6/AD6 P3.0/RxD0 3 46 P0.7/AD7 P3.1/TxD0 4 45 ALE P3.2/INT0 5 44 PSEN/OSCCLK/MODCLK P3.3/INT1/TONE/PWM 6 43 P2.7/A15 P3.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 PIN DESCRIPTIONS PIN # NAME DESCRIPTION 1 XOUT The crystal oscillator pin XOUT supports parallel resonant AT-cut fundamental frequency crystals and ceramic resonators. XOUT serves as the output of the crystal amplifier. 2 XIN 3-10 P3.0-P3.7 The crystal oscillator pin XIN supports parallel resonant AT-cut fundamental frequency crystals and ceramic resonators.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 PIN DESCRIPTIONS (continued) PIN # NAME 44 PSEN OSCCLK MODCLK DESCRIPTION Program Store Enable: Connected to optional external memory as a chip enable. PSEN will provide an active low pulse. In programming mode, PSEN is used as an input along with ALE to define serial or parallel programming mode. PSEN is held high for parallel programming and held low for serial programming.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, filter = Sinc3, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, filter = Sinc3, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, filter = Sinc3, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. ADC INTEGRAL NONLINEARITY vs INPUT SIGNAL ADC INTEGRAL NONLINEARITY vs INPUT SIGNAL ADC INL (ppm of FS) 10 15 AVDD = 5V VREF = 2.5V Buffer ON +85_C 5 0 +125_C +25_C −5 −40_ C −10 −15 −2.5 30 −2 −1.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, filter = Sinc3, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. PGA SUPPLY CURRENT NORMALIZED GAIN vs PGA 101 AVDD = DVDD fCLK = 8MHz VIN = 0V 250 100 AVDD = 5.0V 200 Buffer OFF Normalized Gain (%) PGA Supply Current (µA) 300 150 100 AVDD = 3.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, filter = Sinc3, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. VREFOUT vs LOAD CURRENT 2.510 4000 2.508 3500 2.506 3000 2.504 VREFOUT (V) Number of Occurrences HISTOGRAM OF OUTPUT DATA 4500 2500 2000 1500 2.502 2.500 2.498 2.496 1000 2.494 500 2.492 0 −2 −1.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS: VDACs AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, filter = Sinc3, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. For VDAC: VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF unless otherwise noted. VDAC DIFFERENTIAL NONLINEARITY vs CODE VDAC INTEGRAL NONLINEARITY vs CODE 1.0 40 +125_C 20 0.8 0.6 +85_ C DNL (LSB) INL (LSB) 0.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS: VDACs (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, filter = Sinc3, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. For VDAC: VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF unless otherwise noted. VDAC FULL−SCALE SETTLING TIME Scope Trigger (5.0V/div) VDAC FULL−SCALE SETTLING TIME Scope Trigger (5.
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www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ENHANCED 8051 CORE The MSC1211/12/13/14 also provide dual data pointers (DPTRs) to speed block Data Memory moves. Additionally, both devices can stretch the number of memory cycles to access external Data Memory from between two and nine instruction cycles in order to accommodate different speeds of memory or devices, as shown in Table 2.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Furthermore, improvements were made to peripheral features that off-load processing from the core, and the user, to further improve efficiency. For instance, the SPI interface uses a FIFO, which allows the SPI interface to transmit and receive data with minimum overhead needed from the core.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 OVERVIEW TEMPERATURE SENSOR The MSC1211/12/13/14 ADC structure is shown in Figure 12. The figure lists the components that make up the ADC, along with the corresponding special function register (SFR) associated with each component. On-chip diodes provide temperature sensing capability. When the configuration register for the input MUX is set to all 1s, the diodes are connected to the inputs of the ADC.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ADC ANALOG INPUT When the buffer is not selected, the input impedance of the analog input changes with ACLK clock frequency (ACLK F6h) and gain (PGA). The relationship is: AIN0 AIN1 Impedance (W) + AVDD AIN Impedance (W) + Burnout Detect (2µA) AIN2 1 f SAMP @ CS 10 Ǔ ǒACLK1 Frequency Ǔ @ ǒ7MW PGA 6 where ACLK frequency (f ACLK) + AIN3 In+ and modclk + f MOD + Buffer AIN4 In− AIN7 f ACLK .
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ADC PGA The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128. Using the PGA can actually improve the effective resolution of the ADC. For instance, with a PGA of 1 on a ±2.5V full-scale range (FSR), the ADC can resolve to 1.5µV. With a PGA of 128 on a ±19mV FSR, the ADC can resolve to 75nV, as shown in Table 3. Table 3.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 It will then use the Sinc2 followed by the Sinc3 filter to improve noise performance. This combines the low-noise advantage of the Sinc3 filter with the quick response of the Fast Settling Time filter. The frequency response of each filter is shown in Figure 16. The internal voltage reference can be selected as either 1.25V or 2.5V.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 VDAC DAC OUTPUT AMPLIFIER The architecture of the MSC1211/12/13/14 consists of a string DAC followed by an output buffer amplifier. Figure 17 shows a block diagram of the DAC architecture. The output buffer amplifier is capable of generating rail-to-rail voltages on its output, which provides an output range of AGND to AVDD. It is capable of driving a load of 2kΩ in parallel with 1000pF to GND.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 BIPOLAR OPERATION USING THE DAC ANALOG/DIGITAL LOW-VOLTAGE DETECT The DAC can be used for a bipolar output range, as shown in Figure 18; the circuit illustrates an output voltage range of ±VREF. Rail-to-rail operation at the amplifier output is achievable using an OPA703 as the output amplifier. The MSC1211/12/13/14 contain an analog or digital low-voltage detect.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 POWER ON RESET The on-chip Power On Reset (POR) circuitry releases the device from reset when DVDD ≈ 2.0V. The power supply ramp rate does not affect the POR. If the power supply falls below 1.0V for more than 200ms, then the POR will execute. If the power supply falls below 1.0V for less than 200ms, unexpected operation may occur. If these conditions are not met, the POR will not execute.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 MEMORY MAP FLASH MEMORY The MSC1211/12/13/14 contain on-chip SFR, Flash Memory, Scratchpad SRAM Memory, Boot ROM, and SRAM. The SFR registers are primarily used for control and status. The standard 8051 features and additional peripheral features of the MSC1211/12/13/14 are controlled through the SFR.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 The MSC1211/12/13/14 allow the user to partition the Flash Memory between Program Memory and Data Memory. For instance, the MSC1213Y5 contains 32kB of Flash Memory on-chip. Through the hardware configuration registers, the user can define the partition between Program Memory (PM) and Data Memory (DM), as shown in Table 4 and Table 5. The MSC1211/12/13/14 families offer four memory configurations. Table 4.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 CONFIGURATION MEMORY The MSC121x Configuration Memory consists of 128 bytes. In UAM, all Configuration Memory is readable using the faddr_data_read Boot ROM routine, and the CADDR and CDATA registers. In UAM, however, none of the Configuration Memory is writable. In serial or parallel programming mode, all Configuration Memory is readable.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Thus, an instruction can designate the value stored in R0 (for example) to address the upper RAM. The 16 bytes immediately above the these registers are bit addressable. So any of the 128 bits in this area can be directly accessed using bit addressable instructions.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ACCESSING EXTERNAL MEMORY If external memory is used, P0 and P2 must be configured as address and data lines. If external memory is not used, P0 and P2 can be configured as general-purpose I/O lines through the hardware configuration register (HCR0, HCR1). To enable access to external memory, bits 0 and 1 of the HCR1 register must be set to ‘0’.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Flash Programming Mode There are two programming modes: parallel and serial. The programming mode is selected by the state of the ALE and PSEN signals during reset (BOR, WDT, software, or POR). Serial programming mode is selected with PSEN = 0 and ALE = 1. Parallel programming mode is selected with PSEN = 1 and ALE = 0, as shown in Figure 24.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Table 7.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 INTERRUPTS The MSC1211/12/13/14 use a three-priority interrupt system. As shown in Table 8, each interrupt source has an independent priority bit, flag, interrupt vector, and enable (except that nine interrupts share the Auxiliary Interrupt (AI) at the highest priority). In addition, interrupts can be globally enabled or disabled. The interrupt structure is compatible with the original 8051 family.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Hardware Configuration Register 0 (HCR0)—Accessed Using SFR Registers CADDR and CDATA. CADDR 7Fh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 EPMA PML RSL EBR EWDR DFSEL2 DFSEL1 DFSEL0 NOTE: HCR0 is programmable only in Flash Programming mode, but can be read in User Application mode using the CADDR and CDATA SFRs or the faddr_data_read Boot ROM routine.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Hardware Configuration Register 1 (HCR1) CADDR 7Eh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DBLSEL1 DBLSEL0 ABLSEL1 ABLSEL0 DAB DDB EGP0 EGP23 NOTE: HCR1 is programmable only in Flash Programming mode, but can be read in User Application mode using the CADDR and CDATA SFRs or the faddr_data_read Boot ROM routine. DBLSEL bits 7−6 Digital Supply Brownout Level Select 00: 4.5V 01: 4.2V 10: 2.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Table 9. Special Function Registers NOTE: (Boldface are in addition to standard 8051 registers, and unique to the MSC1211/12/13/14). ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET VALUE 80h P0 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Table 9. Special Function Registers (continued) NOTE: (Boldface are in addition to standard 8051 registers, and unique to the MSC1211/12/13/14).
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Table 9. Special Function Registers (continued) NOTE: (Boldface are in addition to standard 8051 registers, and unique to the MSC1211/12/13/14).
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Table 10. Special Function Register Cross Reference SFR ADDRESS FUNCTIONS CPU INTERRUPTS PORTS SERIAL COMM.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Table 10. Special Function Register Cross Reference (continued) SFR ADDRESS FUNCTIONS CPU INTERRUPTS PORTS SERIAL COMM.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Table 10. Special Function Register Cross Reference (continued) SFR SERIAL COMM.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Port 0 (P0) SFR 80h P0.7−0 bits 7−0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Reset Value P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 FFh Port 0. This port functions as a multiplexed address/data bus during external memory access, and as a generalpurpose I/O port when external memory access is not needed.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Data Pointer Select (DPS) SFR 86h SEL bit 0 7 6 5 4 3 2 1 0 Reset Value 0 0 0 0 0 0 0 SEL 00h Data Pointer Select. This bit selects the active data pointer. 0: Instructions that use the DPTR will use DPL0 and DPH0. 1: Instructions that use the DPTR will use DPL1 and DPH1.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Timer/Counter Control (TCON) SFR 88h 7 6 5 4 3 2 1 0 Reset Value TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00h TF1 bit 7 Timer 1 Overflow Flag. This bit indicates when Timer 1 overflows its maximum count as defined by the current mode. This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 1 interrupt service routine. 0: No Timer 1 overflow has been detected.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Timer Mode Control (TMOD) 7 6 GATE C/T 5 4 3 2 M1 M0 GATE C/T TIMER 1 SFR 89h 1 0 M1 M0 Reset Value TIMER 0 GATE bit 7 Timer 1 Gate Control. This bit enables/disables the ability of Timer 1 to increment. 0: Timer 1 will clock when TR1 = 1, regardless of the state of pin INT1. 1: Timer 1 will clock only when TR1 = 1 and pin INT1 = 1. C/T bit 6 Timer 1 Counter/Timer Select.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Timer 0 MSB (TH0) SFR 8Ch TH0.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value TH0.7 TH0.6 TH0.5 TH0.4 TH0.3 TH0.2 TH0.1 TH0.0 00h Timer 0 MSB. This register contains the most significant byte of Timer 0. Timer 1 MSB (TH1) SFR 8Dh TH1.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value TH1.7 TH1.6 TH1.5 TH1.4 TH1.3 TH1.2 TH1.1 TH1.0 00h Timer 1 MSB.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Memory Write Select (MWS) SFR 8Fh MXWS bit 0 7 6 5 4 3 2 1 0 Reset Value 0 0 0 0 0 0 0 MXWS 00h MOVX Write Select. This allows writing to the internal Flash Program Memory. 0: MOVX operations will access Data Memory (default). 1: MOVX operations will access Program Memory. Write operations can be inhibited by the PML or RSL bits in HCR0. Port 1 (P1) SFR 90h P1.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 External Interrupt Flag (EXIF) SFR 91h 7 6 5 4 3 2 1 0 Reset Value IE5 IE4 IE3 IE2 1 0 0 0 08h IE5 bit 7 External Interrupt 5 Flag. This bit will be set when a falling edge is detected on INT5. This bit must be cleared manually by software. Setting this bit in software will cause an interrupt if enabled. IE4 bit 6 External Interrupt 4 Flag.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Serial Port 0 Control (SCON0) SFR 98h SM0−2 bits 7−5 7 6 5 4 3 2 1 0 Reset Value SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 00h Serial Port 0 Mode. These bits control the mode of serial Port 0. Modes 1, 2, and 3 have 1 start and 1 stop bit in addition to the 8 or 9 data bits.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 SPI Control (SPICON). Any change resets the SPI interface, counters, and pointers. SFR 9Ah SCK bits 7−5 7 6 5 4 3 2 1 0 Reset Value SCK2 SCK1 SCK0 FIFO ORDER MSTR CPHA CPOL 00h SCK Selection. Selection of tCLK divider for generation of SCK in Master mode.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 I2C Control (I2CCON) (Available only on the MSC1211 and MSC1213) SFR 9Ah 7 6 5 4 3 2 1 0 Reset Value START STOP ACK 0 FAST MSTR SCLS FILEN 00h START bit 7 Start Condition (Master mode). Read: Current status of start condition or repeated start condition. Write: When operating as a master, a start condition is transmitted when the START bit is set to 1.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 SPI Receive Control (SPIRCON) SFR 9Ch 7 6 5 4 3 2 1 0 Reset Value RXCNT7 RXFLUSH RXCNT6 RXCNT5 RXCNT4 RXCNT3 RXCNT2 RXIRQ2 RXCNT1 RXIRQ1 RXCNT0 RXIRQ0 00h RXCNT bits 7−0 Receive Counter. Read-only bits which read the number of bytes in the receive buffer (0 to 128). RXFLUSH bit 7 Flush Receive FIFO. Write-only. 0: No Action 1: SPI Receive Buffer Set to Empty RXIRQ bits 2−0 Read IRQ Level.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 SPI Transmit Control (SPITCON) SFR 9Dh 7 6 5 4 3 2 1 0 Reset Value TXCNT7 TXFLUSH TXCNT6 TXCNT5 CLK_EN TXCNT4 DRV_DLY TXCNT3 DRV_EN TXCNT2 TXIRQ2 TXCNT1 TXIRQ1 TXCNT0 TXIRQ0 00h TXCNT bits 7−0 Transmit Counter. Read-only bits which read the number of bytes in the transmit buffer (0 to 128). TXFLUSH bit 7 Flush Transmit FIFO. This bit is write-only.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 I2C Status (I2CSTAT) (Available only on the MSC1211 and MSC1213) SFR 9Dh STAT7−3 bit 7−3 7 6 5 4 3 2 1 0 Reset Value STAT7 SCKD7/SAE STAT6 SCKD6/SA6 STAT5 SCKD5/SA5 STAT4 SCKD4/SA4 STAT3 SCKD3/SA3 0 SCKD2/SA2 0 SCKD1/SA1 0 SCKD0/SA0 00h Status Code. Read-only. Reading this register clears the status interrupt. STATUS CODE STATUS OF THE HARDWARE MODE 0x08 START condition transmitted.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 I2C Start (I2CSTART) (Available only on the MSC1211 and MSC1213) 7 6 5 4 3 2 1 0 SFR 9Eh I2CSTART bits 7−0 Reset Value 80h I2C Start. Write-only. When any value is written to this register, the I2C system is reset; that is, the counters and state machines will go back to the initial state.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 PWM Control (PWMCON) SFR A1h 7 6 5 4 3 2 1 0 Reset Value — — PPOL PWMSEL SPDSEL TPCNTL2 TPCNTL1 TPCNTL0 00h PPOL bit 5 Period Polarity. Specifies the starting level of the PWM pulse. 0: ON Period. PWM Duty register programs the ON period. 1: OFF Period. PWM Duty register programs the OFF period. PWMSEL bit 4 PWM Register Select. Select which 16-bit register is accessed by PWMLOW/PWMHI.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Auxiliary Interrupt Poll (AIPOL) RD SFR A4h 7 6 5 4 3 2 1 ESEC ESUM EADC EMSEC ESPIT ESPIR/EI2C EALV WR 0 Reset Value EDLVB 00h RDSEL 00h Auxiliary interrupts are enabled by EICON.4 (SFR D8h); other interrupts are enabled by the IE and EIE registers. ESEC bit 7 Enable Seconds Timer Interrupt (lowest priority auxiliary interrupt). Read-only. AIPOL.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Pending Auxiliary Interrupt (PAI) SFR A5h PAI3−0 bits 3−0 7 6 5 4 3 2 1 0 Reset Value 0 0 0 0 PAI3 PAI2 PAI1 PAI0 00h Pending Auxiliary Interrupt. The results of this register can be used as an index to vector to the appropriate interrupt routine. All of these interrupts vector through address 0033h.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Auxiliary Interrupt Enable (AIE) SFR A6h 7 6 5 4 3 2 1 0 Reset Value ESEC ESUM EADC EMSEC ESPIT ESPIR/EI2C EALV EDLVB 00h Auxiliary interrupts are enabled by EICON.4 (SFR D8h); other interrupts are enabled by the IE and EIE registers. ESEC bit 7 Enable Seconds Timer Interrupt (lowest priority auxiliary interrupt). Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: When AIPOL.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Auxiliary Interrupt Status (AISTAT) SFR A7h 7 6 5 4 3 2 1 0 Reset Value SEC SUM ADC MSEC SPIT SPIR/I2CSI ALVD DLVD 00h SEC bit 7 Second System Timer Interrupt Status Flag (lowest priority AI). 0: SEC interrupt inactive or masked. 1: SEC Interrupt active. SUM bit 6 Summation Register Interrupt Status Flag.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Interrupt Enable (IE) SFR A8h 7 6 5 4 3 2 1 0 Reset Value EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 00h EA bit 7 Global Interrupt Enable. This bit controls the global masking of all interrupts except those in AIE (SFR A6h). 0: Disable interrupt sources. This bit overrides individual interrupt mask settings for this register. 1: Enable all individual interrupt masks.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Breakpoint Control (BPCON) SFR A9h 7 6 5 4 3 2 1 0 Reset Value BP 0 0 0 0 0 PMSEL EBP 00h Writing to this register sets the breakpoint condition specified by MCON, BPL, and BPH. BP bit 7 Breakpoint Interrupt. This bit indicates that a break condition has been recognized by a hardware breakpoint register(s). Read: Status of Breakpoint Interrupt.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Port 0 Data Direction Low (P0DDRL) SFR ACh P0.3 bits 7−6 P0.2 bits 5−4 P0.1 bits 3−2 P0.0 bits 1−0 7 6 5 4 3 2 1 0 Reset Value P03H P03L P02H P02L P01H P01L P00H P00L 00h Port 0 Bit 3 Control. P03H P03L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 0 Bit 2 Control.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Port 0 Data Direction High (P0DDRH) SFR ADh P0.7 bits 7−6 P0.6 bits 5−4 P0.5 bits 3−2 P0.4 bits 1−0 7 6 5 4 3 2 1 0 Reset Value P07H P07L P06H P06L P05H P05L P04H P04L 00h Port 0 Bit 7 Control. P07H P07L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 0 Bit 6 Control.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Port 1 Data Direction Low (P1DDRL) SFR AEh P1.3 bits 7−6 P1.2 bits 5−4 P1.1 bits 3−2 P1.0 bits 1−0 72 7 6 5 4 3 2 1 0 Reset Value P13H P13L P12H P12L P11H P11L P10H P10L 00h Port 1 Bit 3 Control. P13H P13L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 1 Bit 2 Control.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Port 1 Data Direction High (P1DDRH) SFR AFh P1.7 bits 7−6 P1.6 bits 5−4 P1.5 bits 3−2 P1.4 bits 1−0 7 6 5 4 3 2 1 0 Reset Value P17H P17L P16H P16L P15H P15L P14H P14L 00h Port 1 Bit 7 Control. P17H P17L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 1 Bit 6 Control.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Port 3 (P3) SFR B0h 7 6 5 4 3 2 1 0 Reset Value P3.7 RD P3.6 WR P3.5 T1 P3.4 T0 P3.3 INT1 P3.2 INT0 P3.1 TXD0 P3.0 RXD0 FFh P3.7−0 bits 7−0 General-Purpose I/O Port 3. This register functions as a general-purpose I/O port. In addition, all the pins have an alternative function listed below. Each of the functions is controlled by several other SFRs.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Port 2 Data Direction Low (P2DDRL) SFR B1h P2.3 bits 7−6 P2.2 bits 5−4 P2.1 bits 3−2 P2.0 bits 1−0 7 6 5 4 3 2 1 0 Reset Value P23H P23L P22H P22L P21H P21L P20H P20L 00h Port 2 Bit 3 Control. P23H P23L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 2 Bit 2 Control.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Port 2 Data Direction High (P2DDRH) SFR B2h P2.7 bits 7−6 P2.6 bits 5−4 P2.5 bits 3−2 P2.4 bits 1−0 7 6 5 4 3 2 1 0 Reset Value P27H P27L P26H P26L P25H P25L P24H P24L 00h Port 2 Bit 7 Control. P27H P27L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 2 Bit 6 Control.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Port 3 Data Direction Low (P3DDRL) SFR B3h P3.3 bits 7−6 P3.2 bits 5−4 P3.1 bits 3−2 P3.0 bits 1−0 7 6 5 4 3 2 1 0 Reset Value P33H P33L P32H P32L P31H P31L P30H P30L 00h Port 3 Bit 3 Control. P33H P33L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 3 Bit 2 Control.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Port 3 Data Direction High (P3DDRH) SFR B4h P3.7 bits 7−6 7 6 5 4 3 2 1 0 Reset Value P37H P37L P36H P36L P35H P35L P34H P34L 00h Port 3 Bit 7 Control. P37H P37L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input NOTE: Port 3.7 also controlled by EA and Memory Access Control HCR1.1. P3.6 bits 5−4 Port 3 Bit 6 Control.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 DAC Low Byte (DACL) 7 6 5 4 3 2 1 0 SFR B5h DACL7−0 bits 7−0 Reset Value 00h Least Significant Byte Register for DAC0−3, DAC Control (0 and 2), and DAC Load Control . NOTE: DAC2 and DAC3 available only on the MSC1211 and MSC1212. DAC High Byte (DACH) 7 6 5 4 3 2 1 0 SFR B6h DACH7−0 bits 7−0 Reset Value 00h Most Significant Byte Register for DAC0−3 and DAC Control (1 and 3).
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 DAC0 Control (DACCON0) DACSEL = 04h 7 6 5 4 3 2 1 0 Reset Value SFR B5h COR0 EOD0 IDAC0DIS IDAC0SINK 0 SELREF0 DOM0_1 DOM0_0 63h COR0 bit 7 Current Over Range on DAC0 Write: 0 = Clear to release from high-impedance state back to normal mode unless an over-range condition exists. 1 = NOP Read: 0 = No current over range for DAC0.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 DAC1 Control (DACCON1) DACSEL = 04h 7 6 5 4 3 2 1 0 Reset Value SFR B6h COR1 EOD1 IDAC1DIS IDAC1SINK 0 SELREF1 DOM1_1 DOM1_0 63h COR1 bit 7 Current Over Range on DAC1 Write: 0 = Clear to release from high-impedance state back to normal mode unless an over-range condition exists. 1 = No effect. Read: 0 = No current over range for DAC1. 0 = No effect.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 DAC2 Control (DACCON2) (Available only on the MSC1211 and MSC1212) DACSEL = 05h 7 6 5 4 3 2 1 0 Reset Value SFR B5h 0 0 0 0 0 SELREF2 DOM2_1 DOM2_0 03h SELREF2 bit 2 Select the Reference Voltage for DAC2 Voltage Reference. 0 = DAC2 VREF = AVDD (default). 1 = DAC2 VREF = internal VREF. DOM2_1−0 DAC Output Mode DAC2. bits 1−0 DOM2 OUTPUT MODE for DAC2 00 Normal VDAC output.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 DAC Load Control (LOADCON) DACSEL = 06h 7 6 5 4 3 2 1 0 Reset Value SFR B5h D3LOAD1 D3LOAD0 D2LOAD1 D2LOAD0 D1LOAD1 D1LOAD0 D0LOAD1 D0LOAD0 00h D3LOAD1−0 (Available only on MSC1211 and MSC1212) bit 7−6 The DAC load options are listed below: DxLOAD OUTPUT MODE for 00 Direct load: write to DACxL directly loads the DAC buffer and the DAC output (write to DACxH does not load DAC output).
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Serial Port 1 Control (SCON1) SFR C0h SM0−2 bits 7−5 7 6 5 4 3 2 1 0 Reset Value SM0_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 00h Serial Port 1 Mode. These bits control the mode of serial Port 1. Modes 1, 2, and 3 have 1 start and 1 stop bit in addition to the 8 or 9 data bits.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Enable Wake Up (EWU) Waking Up from Idle Mode SFR C6h 7 6 5 4 3 2 1 0 Reset Value — — — — — EWUWDT EWUEX1 EWUEX0 00h Auxiliary interrupts will wake up from Idle mode. They are enabled with EAI (EICON.5). EWUWDT bit 2 Enable Wake Up Watchdog Timer. Wake using watchdog timer interrupt. 0 = Don’t wake up on watchdog timer interrupt. 1 = Wake up on watchdog timer interrupt.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Timer 2 Control (T2CON) SFR C8h 7 6 5 4 3 2 1 0 Reset Value TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 00h TF2 bit 7 Timer 2 Overflow Flag. This flag will be set when Timer 2 overflows from FFFFh. It must be cleared by software. TF2 will only be set if RCLK and TCLK are both cleared to ‘0’. Writing a ‘1’ to TF2 forces a Timer 2 interrupt if enabled. EXF2 bit 6 Timer 2 External Flag.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Timer 2 Capture MSB (RCAP2H) 7 6 5 4 3 2 1 0 Reset Value SFR CBh RCAP2H bits 7−0 00h Timer 2 Capture MSB. This register is used to capture the TH2 value when Timer 2 is configured in capture mode. RCAP2H is also used as the MSB of a 16-bit reload value when Timer 2 is configured in auto-reload mode. Timer 2 LSB (TL2) 7 6 5 4 3 2 1 0 Reset Value SFR CCh TL2 bits 7−0 00h Timer 2 LSB.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ADC Offset Calibration Low Byte (OCL) 7 6 5 4 3 2 1 0 Reset Value SFR D1h OCL bits 7−0 00h ADC Offset Calibration Low Byte. This is the low byte of the 24-bit word that contains the ADC offset calibration. A value that is written to this location will set the ADC offset calibration value.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ADC Input Multiplexer (ADMUX) SFR D7h INP3−0 bits 7−4 INN3−0 bits 3−0 7 6 5 4 3 2 1 0 Reset Value INP3 INP2 INP1 INP0 INN3 INN2 INN1 INN0 01h Input Multiplexer Positive Input. This selects the positive signal input.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Enable Interrupt Control (EICON) SFR D8h 7 6 5 4 3 2 1 0 Reset Value SMOD1 1 EAI AI WDTI 0 0 0 40h SMOD1 bit 7 Serial Port 1 Mode. When this bit is set the serial baud rate for Port 1 will be doubled. 0 = Standard baud rate for Port 1 (default). 1 = Double baud rate for Port 1. EAI bit 5 Enable Auxiliary Interrupt.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ADC Control 0 (ADCON0) SFR DCh REFCLK bit 7 7 6 5 4 3 2 1 0 Reset Value REFCLK BOD EVREF VREFH EBUF PGA2 PGA1 PGA0 30h Reference Clock. The reference is specified with a 250kHz clock. The REFCLK should be selected by choosing the appropriate source so that it does not exceed 250kHz. t CLK (ACLK ) 1) * 4 1 + USEC 4 0+ BOD bit 6 Burnout Detect.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ADC Control 1 (ADCON1) SFR DDh 7 6 5 4 3 2 1 0 Reset Value OF_UF POL SM1 SM0 — CAL2 CAL1 CAL0 0000 0000b OF_UF bit 7 Overflow/Underflow. If this bit is set, the data in the summation register is invalid. Either an overflow or underflow occurred. The bit is cleared by writing a ‘0’ to it. POL bit 6 Polarity. Polarity of the ADC result and Summation register. 0 = Bipolar. 1 = Unipolar.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Accumulator (A or ACC) SFR E0h ACC.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 00h Accumulator. This register serves as the accumulator for arithmetic and logic operations.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Summation 0 (SUMR0) 7 6 5 4 3 2 1 0 SFR E2h SUMR0 bits 7−0 Reset Value 00h Summation 0. This is the least significant byte of the 32-bit summation register, or bits 0 to 7. Write: values in SUMR3−0 are added to the summation register. Read: clears the Summation Count Interrupt; however, AI in EICON (SFR D8) must also be cleared.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Low Voltage Detect Control (LVDCON) SFR E7h 7 6 5 4 3 2 1 0 Reset Value ALVDIS ALVD2 ALVD1 ALVD0 DLVDIS DLVD2 DLVD1 DLVD0 00h ALVDIS bit 7 Analog Low Voltage Detect Disable. 0 = Enable Detection of Low Analog Supply Voltage. 1 = Disable Detection of Low Analog Supply Voltage. ALVD2−0 bits 6−4 Analog Voltage Detection Level. ALVD2 ALVD1 ALVD0 VOLTAGE LEVEL 0 0 0 0 0 1 AVDD 2.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Extended Interrupt Enable (EIE) SFR E8h 7 6 5 4 3 2 1 0 Reset Value 1 1 1 EWDI EX5 EX4 EX3 EX2 E0h EWDI bit 4 Enable Watchdog Interrupt. This bit enables/disables the watchdog interrupt. The Watchdog timer is enabled by (SFR FFh) and PDCON (SFR F1h) registers. 0 = Disable the Watchdog Interrupt 1 = Enable Interrupt Request Generated by the Watchdog Timer EX5 bit 3 External Interrupt 5 Enable.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Hardware Version (HDWVER) 7 6 5 4 3 2 1 0 Reset Value SFR EBh Flash Memory Control (FMCON) SFR EEh 7 6 5 4 3 2 1 0 Reset Value 0 PGERA 0 FRCM 0 BUSY SPM FPM 02h PGERA bit 6 Page Erase. Available in both user and program modes. 0 = Disable Page Erase Mode 1 = Enable Page Erase Mode (automatically set by page_erase Boot ROM routine). FRCM bit 4 Frequency Control Mode.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Power-Down Control (PDCON) SFR F1h 7 6 5 4 3 2 1 0 Reset Value 0 PDDAC PDI2C PDPWM PDADC PDWDT PDST PDSPI 7Fh Turning peripheral modules off puts the MSC1211/12/13/14 in the lowest power mode. PDDAC bit 6 DAC Module Control. 0 = DACs On 1 = DACs Power Down PDI2C bit 5 I2C Control (MSC1211 and MSC1213 only).
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Analog Clock (ACLK) SFR F6h 7 6 5 4 3 2 1 0 Reset Value 0 FREQ6 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 03h FREQ6−0 Clock Frequency Selection. This value + 1 divides the system clock to create the ACLK frequency.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Seconds Timer Interrupt (SECINT) SFR F9h 7 6 5 4 3 2 1 0 Reset Value WRT SECINT6 SECINT5 SECINT4 SECINT3 SECINT2 SECINT1 SECINT0 7Fh This system clock is divided by the value of the 16-bit register MSECH:MSECL. Then, that 1ms timer tick is divided by the register HMSEC which provides the 100ms signal used by this seconds timer.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 One Millisecond Timer High Byte (MSECH) SFR FDh 7 6 5 4 3 2 1 0 Reset Value MSECH7 MSECH6 MSECH5 MSECH4 MSECH3 MSECH2 MSECH1 MSECH0 0Fh MSECH7−0 One Millisecond Timer High Byte. This value in combination with the previous register is used to create a 1ms clock. bits 7−0 1ms = (MSECH • 256 + MSECL + 1) • tCLK.
www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Revision History DATE REV PAGE SECTION 10/07 G 29 Voltage Reference 7/06 F 32 Brownout Reset DESCRIPTION Added paragraph to end of section. Added paragraph on BOR voltage calibration. NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com 21-Mar-2013 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production.
PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant MSC1211Y2PAGT TQFP PAG 64 250 330.0 24.8 13.0 13.0 1.5 16.0 24.0 Q2 MSC1211Y3PAGT TQFP PAG 64 250 330.0 24.8 13.0 13.0 1.5 16.0 24.0 Q2 MSC1211Y4PAGT TQFP PAG 64 250 330.0 24.8 13.0 13.0 1.5 16.0 24.
PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSC1211Y2PAGT TQFP PAG 64 250 367.0 367.0 45.0 MSC1211Y3PAGT TQFP PAG 64 250 367.0 367.0 45.0 MSC1211Y4PAGT TQFP PAG 64 250 367.0 367.0 45.0 MSC1211Y5PAGR TQFP PAG 64 1500 367.0 367.0 45.0 MSC1211Y5PAGT TQFP PAG 64 250 367.0 367.0 45.0 MSC1212Y3PAGT TQFP PAG 64 250 367.0 367.0 45.
MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 48 0,08 M 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4040282 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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