Datasheet

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MSP430AFE2x3

MSP430AFE2x2

MSP430AFE2x1

www.ti.com

SLAS701A –NOVEMBER 2010–REVISED MARCH 2011

MIXED SIGNAL MICROCONTROLLER

FEATURES

• Low Supply Voltage Range: 1.8 V to 3.6 V • Up to Three 24-Bit Sigma-Delta

Analog-to-Digital (A/D) Converters With

• Ultra-Low Power Consumption

Differential PGA Inputs

– Active Mode: 220 µA at 1 MHz, 2.2 V

• 16-Bit Timer_A With Three Capture/Compare

– Standby Mode: 0.5 µA

Registers

– Off Mode (RAM Retention): 0.1 µA

• Serial Communication Interface (USART),

• Five Power-Saving Modes

Asynchronous UART or Synchronous SPI

• Ultra-Fast Wake-Up From Standby Mode in

Selectable by Software

Less Than 1 µs

• 16-Bit Hardware Multiplier

• 16-Bit RISC Architecture, up to 12-MHz System

• Brownout Detector

Clock

• Supply Voltage Supervisor/Monitor with

• Basic Clock Module Configurations

Programmable Level Detection

– Internal Frequencies up to 12 MHz With

• Serial Onboard Programming, No External

Two Calibrated Frequencies

Programming Voltage Needed Programmable

– Internal Very-Low-Power Low-Frequency

Code Protection by Security Fuse

(LF) Oscillator

• On-Chip Emulation Module

– High-Frequency (HF) Crystal up to 16 MHz

• Family Members are Summarized in Table 1.

– Resonator

• For Complete Module Descriptions, See the

– External Digital Clock Source

MSP430x2xx Family User's Guide, Literature

Number SLAU144

DESCRIPTION

The Texas Instruments MSP430™ family of ultra-low-power microcontrollers consists of several devices featuring

different sets of peripherals targeted for various applications. The architecture, combined with five low-power

modes, is optimized to achieve extended battery life in portable measurement applications. The device features a

powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.

The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs.

The MSP430AFE2x3 devices are ultra-low-power mixed signal microcontrollers integrating three independent

24-bit sigma-delta A/D converters, one 16-bit timer, one 16-bit hardware multiplier, USART communication

interface, watchdog timer, and 11 I/O pins.

The MSP430AFE2x2 devices are identical to the MSP430AFE2x3, except that there are only two 24-bit

sigma-delta A/D converters integrated.

The MSP430AFE2x1 devices are identical to the MSP430AFE2x3, except that there is only one 24-bit

sigma-delta A/D converter integrated.

Available family members are summarized in Table 1.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (47 pages)

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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com MIXED SIGNAL MICROCONTROLLER FEATURES 1 • • • • • • Low Supply Voltage Range: 1.8 V to 3.6 V Ultra-Low Power Consumption – Active Mode: 220 µA at 1 MHz, 2.2 V – Standby Mode: 0.5 µA – Off Mode (RAM Retention): 0.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com Table 1.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com Functional Block Diagram XT2IN XT2OUT DVCC DVSS AVCC AVSS ACLK Basic Clock System+ SMCLK MCLK 12MHz CPU MAB incl. 16 Registers MDB 16KB 8KB 4KB 512B 512B 256B Flash RAM BOR Watchdog WDT+ 15/16-bit P1.x 8 Hardware Multiplier (16x16) P2.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com Pin Designation, MSP430AFE2x2IPW A0.0+ 1 24 P2.0/STE0/TA0/TDI/TCLK A0.0- 2 23 P1.7/UCLK0/TA1/TDO/TDI A1.0+ 3 22 P1.6/SOMI0/TA2/TCK A1.0- 4 21 P1.5/SIMO0/SVSOUT/TMS AVCC 5 20 P1.4/URXD0 AVSS 6 19 P1.3/UTXD0/SD1DO VREF 7 18 P1.2/TA0/SD0DO NC 8 17 P1.1/TA1/SDCLK NC 9 16 DVCC TEST/SBWTCK 10 15 P2.7/XT2OUT RST/NMI/SBWTDIO 11 14 P2.6/XT2IN P1.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com Table 2. Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION A0.0+ 1 I SD24_A positive analog input A0.0 (1) A0.0- 2 I SD24_A negative analog input A0.0 (1) A1.0+ 3 I SD24_A positive analog input A1.0 (not available on MSP430AFE2x1) (1) A1.0- 4 I SD24_A negative analog input A1.0 (not available on MSP430AFE2x1) (1) AVCC 5 Analog supply voltage, positive terminal.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com Table 2. Terminal Functions (continued) TERMINAL NAME P2.0/STE0/TA0/TDI/TCLK 6 NO. 24 Submit Documentation Feedback I/O I/O DESCRIPTION General-purpose digital I/O pin Slave transmit enable - USART0/SPI mode. Timer_A3, compare: Out0 output JTAG test data input or test clock input for device programming and test.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com SHORT-FORM DESCRIPTION CPU The MSP430™ CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com Operating Modes The MSP430 microcontrollers have one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: • Active mode ( AM) – All clocks are active.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com Interrupt Vector Addresses The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, if flash is not programmed), the CPU goes into LPM4 immediately after power up. Table 5.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com Special Function Registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. Legend rw rw-0, 1 rw-(0), (1) Bit can be read and written. Bit can be read and written. It is Reset or Set by PUC.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com Table 10. Module Enable Register 1 Address 7 6 04h UTXE0 URXE0 USPIE0 rw-0 rw-0 URXE0 UTXE0 USPIE0 5 4 3 2 1 0 2 1 0 USART0: UART mode receive enable USART0: UART mode transmit enable USART0: SPI mode transmit and receive enable Table 11. Module Enable Register 2 Address 7 6 5 4 3 05h Memory Organization Table 12.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com Peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com Timer_A3 Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 14.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com Peripheral File Map Table 15.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com Table 16.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com Absolute Maximum Ratings (1) Voltage applied at VCC to VSS -0.3 V to 4.1 V Voltage applied to any pin (2) -0.3 V to VCC + 0.3 V ±2 mA Diode current at any device terminal Storage temperature, Tstg (3) (1) (2) (3) Unprogrammed device -55°C to 150°C Programmed device -40°C to 85°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com Low-Power-Mode Supply Currents (Into VCC) Excluding External Current PARAMETER TA VCC Low-power mode 0 (LPM0) current (2) fMCLK = 0 MHz, fSMCLK = fDCO = DCO default frequency (approximately 1 MHz), fACLK = fVLO = 12 kHz, CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 25°C 2.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com Schmitt-Trigger Inputs (Ports Px and RST/NMI) PARAMETER TEST CONDITIONS VIT+ Positive-going input threshold voltage VIT- Negative-going input threshold voltage Vhys Input voltage hysteresis (VIT+ - VIT-) RPull Pullup/pulldown resistor (not RST/NMI pin) For pullup: VIN = VSS; For pulldown: VIN = VCC CI Input capacitance VIN = VSS or VCC VCC MIN TYP MAX UNIT 0.45 VCC 0.75 VCC 1.35 2.25 0.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com Typical Characteristics – Outputs One output loaded at a time. TYPICAL LOW -LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOL TAGE TYPICAL LOW -LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOL TAGE 50.0 VCC = 2.2 V P1.0 TA = 25°C 20.0 I OL − Typical Low-Level Output Current − mA I OL − Typical Low-Level Output Current − mA 25.0 TA = 85°C 15.0 10.0 5.0 0.0 0.0 0.5 1.0 1.5 2.0 VCC = 3 V P1.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com POR/Brownout Reset (BOR) (1) (2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VCC(start) See Figure 9 dVCC/dt ≤ 3 V/s 0.7 × V(B_IT-) V(B_IT-) See Figure 9 through Figure 11 dVCC/dt ≤ 3 V/s 1.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com Typical Characteristics – POR/Brownout Reset (BOR) VCC 3V 2 VCC(drop) − V VCC = 3 V Typical Conditions t pw 1.5 1 VCC(drop) 0.5 0 0.001 1 1000 1 ns t pw − Pulse Width − µs 1 ns t pw − Pulse Width − µs Figure 10. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal VCC 2 t pw 3V VCC(drop) − V VCC = 3 V 1.5 Typical Conditions 1 VCC(drop) 0.5 0 0.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com Supply Voltage Supervisor (SVS) / Supply Voltage Monitor (SVM) (1) PARAMETER TEST CONDITIONS MIN dVCC/dt > 30 V/ms (see Figure 12) t(SVSR) VLD ≉ 0 V(SVSstart) VLD ≉ 0, VCC/dt ≤ 3 V/s (see Figure 12) VCC/dt ≤ 3 V/s (see Figure 12) Vhys(SVS_IT-) VCC/dt ≤ 3 V/s (see Figure 12), external voltage applied on SVSIN VLD = 1 VLD = 2 to 14 15 mV VLD = 15 10 mV 1.8 2.1 VLD = 3 2.2 VLD = 4 2.3 2.24 2.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com Typical Characteristics – SVS Software sets VLD > 0: SVS is active AVCC V(SVS_IT-- ) V(SVSstart) Vhys(SVS_IT-- ) Vhys(B_IT-- ) V(B_IT-- ) VCC(start) Brownout Brownout Region Brownout Region 1 0 SVS out t d(BOR) SVS CircuitisActiveFromVLD>toV 1 0 td(SVSon) Set POR 1 CC td(BOR) < V(B_IT-- ) td(SVSR) undefined 0 Figure 12.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com Main DCO Characteristics • • • All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15. DCO control bits DCOx have a step size as defined by parameter SDCO. Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com Calibrated DCO Frequencies – Tolerance PARAMETER TA VCC MIN TYP MAX UNIT 8-MHz tolerance over temperature (1) BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, calibrated at 30°C and 3.3V 0°C to 85°C 3.3 V 7.76 8 8.24 MHz 8-MHz tolerance over VCC BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, calibrated at 30°C and 3.3V 30°C 2.7 V to 3.6 V 7.76 8 8.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com Internal Very-Low-Power Low-Frequency Oscillator (VLO) TA VCC MIN TYP MAX fVLO VLO frequency PARAMETER -40°C to 85°C 3V 4 12 22 dfVLO/dT VLO frequency temperature drift (1) -40°C to 85°C 3V dfVLO/dVCC VLO frequency supply voltage drift (2) 25°C 1.8 V to 3.6 V (1) (2) UNIT kHz 0.5 %/°C 4 %/V Calculated using the box method: [MAX(-40...85°C) - MIN(-40...85°C)]/MIN(-40...
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com Typical Characteristics – XT2 Oscillator 100000.00 1800.0 LFXT1Sx = 2 10000.00 1000.00 LFXT1Sx = 2 100.00 XT Oscillator Supply Current − uA Oscillation Allowance − Ohms 1600.0 1400.0 1200.0 1000.0 800.0 600.0 400.0 LFXT1Sx = 1 LFXT1Sx = 1 200.0 LFXT1Sx = 0 10.00 0.10 1.00 10.00 100.00 0.0 0.0 LFXT1Sx = 0 4.0 Crystal Frequency − MHz 8.0 12.0 16.0 20.0 Crystal Frequency − MHz Figure 15.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com SD24_A, Temperature Sensor and Built-In VCC Sense PARAMETER TEST CONDITIONS TCSensor Sensor temperature coefficient VOffset,sensor Sensor offset voltage Sensor output voltage (1) (2) VCC,Sense VCC divider at input 5 RSource,VCC Source resistance of VCC divider at input 5 (2) MIN TYP MAX 1.18 1.32 1.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com SD24_A, External Reference Input VCC MIN TYP MAX VREF(I) Input voltage range PARAMETER SD24REFON = 0 TEST CONDITIONS 3V 1.0 1.25 1.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com RAM over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER V(RAMh) (1) RAM retention supply voltage TEST CONDITIONS (1) MIN CPU halted MAX UNIT 1.6 V This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should happen during this supply voltage condition.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com APPLICATION INFORMATION Port P1 Pin Schematic: P1.0 Input/Output With Schmitt Trigger Pad Logic To SVS Mux VLD = 15 P1REN.0 DVSS 0 DVCC 1 1 0 P1DIR.0 P1SEL2.0 Direction 0: Input 1: Output 1 From Timer_A3 0 SMCLK 1 1 P1OUT.0 0 P1.0/SVSIN/TACLK/SMCLK/TA2 Bus Keeper EN P1SEL.0 P1IN.0 EN To Timer_A3 D P1IE.0 P1IRQ.0 EN Q Set P1IFG.0 P1SEL.0 Interrupt Edge Select P1IES.0 Table 17.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com Port P1 Pin Schematic: P1.1 and P1.2 Input/Output With Schmitt Trigger Pad Logic P1REN.x From SD24_A 0 DVCC 1 1 0 P1DIR.x P1SEL2.x From Timer_A3 DVSS Direction 0: Input 1: Output 1 0 1 1 P1OUT.x 0 P1.1/TA1/SDCLK P1.2/TA0/SD0DO Bus Keeper EN P1SEL.x P1IN.x EN To Timer_A3 D P1IE.x P1IRQ.x EN Q Set P1IFG.x P1SEL.x P1IES.x Interrupt Edge Select Table 18. Port P1 (P1.1 and P1.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com Port P1 Pin Schematic: P1.3 Input/Output With Schmitt Trigger Pad Logic P1REN.3 DVSS 0 DVCC 1 P1DIR.3 1 0 1 Direction 0: Input 1: Output 1 USART0 direction 0 SD24_A data 1 USART0 data out 0 P1OUT.3 0 1 P1.3/UTXD0/SD1DO P1SEL.3 P1SEL2.3 Bus Keeper EN P1IN.3 EN Not used D P1IE.3 EN P1IRQ.3 Q Set P1IFG.3 P1SEL.3 P1IES.3 Interrupt Edge Select Table 19. Port P1 (P1.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com Port P1 Pin Schematic: P1.4 Input/Output With Schmitt Trigger Pad Logic P1REN.4 DVSS 0 DVCC 1 P1DIR.4 1 0 1 Direction 0: Input 1: Output 1 USART0 direction 0 P1SEL2.4 P1OUT.4 0 SD24_A data 1 P1.4/URXD0/SD2DO P1SEL.4 Bus Keeper EN P1IN.4 EN USART0 data in D P1IE.4 P1IRQ.4 EN Q Set P1IFG.4 P1SEL.4 P1IES.4 Interrupt Edge Select Table 20. Port P1 (P1.4) Pin Functions PIN NAME (P1.x) x P1.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com Port P1 Pin Schematic: P1.5 to P1.7 Input/Output With Schmitt Trigger Pad Logic P1REN.x P1DIR.x Direction 0: Input 1: Output 0 DVSS 0 DVCC 1 1 1 1 USART0 direction 0 Module X out 1 P1OUT.x USART0 data out 0 1 0 P1SEL.x P1SEL2.x P1.5/SIMO0/SVSOUT/TMS P1.6/SOMI0/TA2/TCK P1.7/UCLK0/TA1/TDO/TDI Bus Keeper EN P1IN.x EN USART0 data in D P1IE.x P1IRQ.x EN Q Set P1IFG.x P1SEL.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com Port P2 Pin Schematic: P2.0 Input/Output With Schmitt Trigger P2REN.0 Pad Logic P2DIR.0 Direction 0: Input 1: Output 0 DVSS 0 DVCC 1 1 1 1 USART0 direction 0 Timer_A3 out 1 USART0 data out 0 P2OUT.0 0 1 P2.0/STE0/TA0/TDI/TCLK P2SEL.0 P2SEL2.0 Bus Keeper EN P2IN.0 EN USART0 data in D P2IE.0 EN P2IRQ.0 Q Set P2IFG.0 P2SEL.0 P2IES.0 Interrupt Edge Select To JTAG From JTAG Table 22.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger BCSCTL3.XT2Sx = 11 P2.7/XT2OUT XT2 off 0 XT2CLK 1 P2SEL.7 Pad Logic P2REN.6 P2DIR.6 DVSS 0 DVCC 1 1 0 Direction 0: Input 1: Output 1 P2OUT.6 0 Module X OUT 1 P2.6/XT2IN Bus Keeper EN P2SEL.6 P2IN.6 EN Module X IN D P2IE.6 EN P2IRQ.6 Q Set P2IFG.6 P2SEL.6 P2IES.6 Interrupt Edge Select Table 23. Port P2 (P2.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger BCSCTL3.XT2Sx = 11 P2.6/XT2IN XT2 off 0 XT2CLK From P2.6/XT2IN 1 P2SEL.6 Pad Logic P2REN.7 P2DIR.7 DVSS 0 DVCC 1 1 0 Direction 0: Input 1: Output 1 P2OUT.7 0 Module X OUT 1 P2.7/XT2OUT Bus Keeper EN P2SEL.7 P2IN.7 EN Module X IN D P2IE.7 P2IRQ.7 EN Q Set P2IFG.7 P2SEL.7 P2IES.7 Interrupt Edge Select Table 24. Port P2 (P2.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.com JTAG Fuse Check Mode MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current, ITF , of 1 mA at 3 V or 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned.
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1 SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011 www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 2-Apr-2012 Status (1) Package Type Package Drawing Pins MSP430AFE253IPWR ACTIVE TSSOP PW 24 XMS430AFE253IPWR OBSOLETE TSSOP PW 24 Package Qty 2000 Eco Plan (2) Green (RoHS & no Sb/Br) TBD Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CU NIPDAU Level-1-260C-UNLIM Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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