Datasheet

Direction
0: Input
1: Output
P1SEL.0
P1DIR.0
P1IN.0
P1IRQ.0
D
EN
To Timer_A3
From Timer_A3
P1OUT.0
Interrupt
Edge Select
Q
EN
Set
P1SEL.0
P1IES.0
P1IFG.0
P1IE.0
DVSS
DVCC
P1REN.0
Pad Logic
1
1
0
0
1
1
0
P1.0/SVSIN/TACLK/SMCLK/TA2
1
0
SMCLK
P1SEL2.0
Bus
Keeper
EN
To SVS Mux
VLD = 15
MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
www.ti.com SLAS701A –NOVEMBER 2010–REVISED MARCH 2011
APPLICATION INFORMATION
Port P1 Pin Schematic: P1.0 Input/Output With Schmitt Trigger
Table 17. Port P1 (P1.0) Pin Functions
CONTROL BITS / SIGNALS
(1)
PIN NAME (P1.x) x FUNCTION
P1DIR.x P1SEL.x P1SEL2.x
P1.0 (I/O) I: 0, O: 1 0 X
SVSIN (VLD = 15) X X X
P1.0/SVSIN/TACLK/SMCLK/TA2 0 Timer_A3.TACLK 0 1 0
SMCLK 1 1 1
Timer_A3.TA2 1 1 0
(1) X = don't care
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