Datasheet

MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
www.ti.com SLAS701A –NOVEMBER 2010–REVISED MARCH 2011
Table 16. Peripherals With Byte Access
SD24_A Channel 0 Input Control SD24INCTL0 0x00B0
(also see Table 15)
Channel 1 Input Control SD24INCTL1 0x00B1
Channel 2 Input Control SD24INCTL2 0x00B2
Channel 0 Preload SD24PRE0 0x00B8
Channel 1 Preload SD24PRE1 0x00B9
Channel 2 Preload SD24PRE2 0x00BA
Reserved (Internal SD24_A Configuration 1) SD24CONF1 0x00BF
USART0 Transmit buffer U0TXBUF 0x0077
Receive buffer U0RXBUF 0x0076
Baud rate U0BR1 0x0075
Baud rate U0BR0 0x0074
Modulation control U0MCTL 0x0073
Receive control U0RCTL 0x0072
Transmit control U0TCTL 0x0071
USART control U0CTL 0x0070
Basic Clock System+ Basic clock system control 3 BCSCTL3 0x0053
Basic clock system control 2 BCSCTL2 0x0058
Basic clock system control 1 BCSCTL1 0x0057
DCO clock frequency control DCOCTL 0x0056
Brownout, SVS SVS control register (reset by brownout signal) SVSCTL 0x0055
Port P2 Port P2 selection 2 P2SEL2 0x0042
Port P2 resistor enable P2REN 0x002F
Port P2 selection P2SEL 0x002E
Port P2 interrupt enable P2IE 0x002D
Port P2 interrupt edge select P2IES 0x002C
Port P2 interrupt flag P2IFG 0x002B
Port P2 direction P2DIR 0x002A
Port P2 output P2OUT 0x0029
Port P2 input P2IN 0x0028
Port P1 Port P1 selection 2 register P1SEL2 0x0041
Port P1 resistor enable P1REN 0x0027
Port P1 selection P1SEL 0x0026
Port P1 interrupt enable P1IE 0x0025
Port P1 interrupt edge select P1IES 0x0024
Port P1 interrupt flag P1IFG 0x0023
Port P1 direction P1DIR 0x0022
Port P1 output P1OUT 0x0021
Port P1 input P1IN 0x0020
Special Function SFR module enable 2 ME2 0x0005
SFR module enable 1 ME1 0x0004
SFR interrupt flag 2 IFG2 0x0003
SFR interrupt flag 1 IFG1 0x0002
SFR interrupt enable 2 IE2 0x0001
SFR interrupt enable 1 IE1 0x0000
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