Datasheet

MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
www.ti.com SLAS701A –NOVEMBER 2010–REVISED MARCH 2011
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
PARAMETER T
A
V
CC
MIN TYP MAX UNIT
f
VLO
VLO frequency -40°C to 85°C 3 V 4 12 22 kHz
df
VLO
/dT VLO frequency temperature drift
(1)
-40°C to 85°C 3 V 0.5 %/°C
df
VLO
/dV
CC
VLO frequency supply voltage drift
(2)
25°C 1.8 V to 3.6 V 4 %/V
(1) Calculated using the box method: [MAX(-40...85°C) - MIN(-40...85°C)]/MIN(-40...85°C)/[85°C - (-40°C)]
(2) Calculated using the box method: [MAX(1.8...3.6 V) - MIN(1.8...3.6 V)]/MIN(1.8...3.6 V)/(3.6 V - 1.8 V)
Crystal Oscillator (XT2)
(1)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
XT2 oscillator crystal frequency,
f
XT2,HF0
XT2OFF = 0, XT2Sx = 0 1.8 V to 3.6 V 0.4 1 MHz
HF mode 0
XT2 oscillator crystal frequency,
f
XT2,HF1
XT2OFF = 0, XT2Sx = 1 1.8 V to 3.6 V 1 4 MHz
HF mode 1
1.8 V to 2.2 V 2 10
XT2 oscillator crystal frequency,
f
XT2,HF2
XT2OFF = 0, XT2Sx = 2 2.2 V to 3.0 V 2 12 MHz
HF mode 2
3.0 V to 3.6 V 2 16
1.8 V to 2.2 V 0.4 10
XT2 oscillator logic-level
f
XT2,HF,logic
square-wave input frequency, XT2OFF = 0, XT2Sx = 3 2.2 V to 3.0 V 0.4 12 MHz
HF mode
3.0 V to 3.6 V 0.4 16
XT2OFF = 0, XT2Sx = 0
f
XT2,HF
= 1 MHz, 2700
C
L,eff
= 15 pF
Oscillation allowance for HF XT2OFF = 0, XT2Sx = 1
OA
HF
crystals (see Figure 15 and f
XT2,HF
= 4 MHz, 800 Ω
Figure 16) C
L,eff
= 15 pF
XT2OFF = 0, XT2Sx = 2
f
XT2,HF
= 16 MHz, 300
C
L,eff
= 15 pF
Integrated effective load
C
L,eff
XT2OFF = 0
(3)
1 pF
capacitance, HF mode
(2)
XT2OFF = 0, Measured at
P1.0/SVSIN/TACLK/SMCLK/TA2, 40 50 60
f
XT2,HF
= 10 MHz
Duty cycle 3 V %
XT2OFF = 0, Measured at
P1.0/SVSIN/TACLK/SMCLK/TA2, 40 50 60
f
XT2,HF
= 16 MHz
f
Fault,HF
Oscillator fault frequency
(4)
XT2OFF = 0, XT2Sx = 3
(5)
3 V 30 300 kHz
(1) To improve EMI on the XT2 oscillator the following guidelines should be observed:
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.
(d) Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
(2) Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it is
recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should
always match the specification of the used crystal.
(3) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(4) Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and
frequencies in between might set the flag.
(5) Measured with logic-level input frequency, but also applies to operation with crystals.
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