Datasheet

To JTAG
From JTAG
Direction
0: Input
1: Output
P1SEL.x
P1DIR.x
P1IN.x
P1IRQ.x
D
EN
P1OUT.x
Interrupt
Edge Select
Q
EN
Set
P1SEL.x
P1IES.x
P1IFG.x
P1IE.x
DVSS
DVCC
P1REN.x
Pad Logic
1
1
0
1
0
1
0
Bus
Keeper
ENEN
P1.5/SIMO0/SVSOUT/TMS
P1.6/SOMI0/TA2/TCK
P1.7/UCLK0/TA1/TDO/TDI
0
1
0
1
P1SEL2.x
USART0
direction
USART0
data out
Module X out
USART0
data in
From JTAG (TDO)
From JTAG
MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
www.ti.com SLAS701A –NOVEMBER 2010–REVISED MARCH 2011
Port P1 Pin Schematic: P1.5 to P1.7 Input/Output With Schmitt Trigger
Table 21. Port P1 (P1.5 to P1.7) Pin Functions
CONTROL BITS / SIGNALS
(1)
PIN NAME (P1.x) x FUNCTION
JTAG
P1DIR.x P1SEL.x P1SEL2.x
Mode
(2)
5 P1.5 (I/O) I: 0; O: 1 0 X 0
SIMO0 X 1 0 0
P1.5/SIMO0/SVSOUT/TMS
SVSOUT 1 1 1 0
TMS X X X 1
6 P1.6 (I/O) I: 0; O: 1 0 X 0
SOMI0 X 1 0 0
P1.6/SOMI0/TA2/TCK
Timer_A3.TA2 1 1 1 0
TCK X X X 1
7 P1.7 (I/O) I: 0; O: 1 0 X 0
UCLK0 X 1 0 0
P1.7/UCLK0/TA1/TDO/TDI
Timer_A3.TA1 1 1 1 0
TDO/TDI X X X 1
(1) X = don't care
(2) JTAG Mode is not a register bit but signal generated internally when 4-wire JTAG option is selected in IDE
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