Datasheet

To JTAG
From JTAG
Direction
0: Input
1: Output
P2SEL.0
P2DIR.0
P2IN.0
P2IRQ.0
D
EN
P2OUT.0
Interrupt
Edge Select
Q
EN
Set
P2SEL.0
P2IES.0
P2IFG.0
P2IE.0
DVSS
DVCC
P2REN.0
Pad Logic
1
1
0
1
0
1
0
Bus
Keeper
ENEN
P2.0/STE0/TA0/TDI/TCLK
0
1
0
1
P2SEL2.0
USART0
direction
USART0
data out
Timer_A3 out
USART0
data in
MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A – NOVEMBER 2010– REVISED MARCH 2011 www.ti.com
Port P2 Pin Schematic: P2.0 Input/Output With Schmitt Trigger
Table 22. Port P2 (P2.0) Pin Functions
CONTROL BITS / SIGNALS
(1)
PIN NAME (P2.x) x FUNCTION
JTAG
P2DIR.x P2SEL.x P2SEL2.x
Mode
(2)
0 P2.0 (I/O) I: 0; O: 1 0 X 0
STE0 X 1 0 0
P2.0/STE0/TA0/TDI/TCLK
Timer_A3.TA0 1 1 1 0
TDI/TCLK X X X 1
(1) X = don't care
(2) JTAG Mode is not a register bit but signal generated internally when 4-wire JTAG option is selected in IDE
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