Datasheet

MSP430BT5190
www.ti.com SLAS703A –APRIL 2010–REVISED AUGUST 2013
TB0
TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. It can support multiple
capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may
be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 11. TB0 Signal Connections
INPUT PIN
MODULE DEVICE
OUTPUT PIN NUMBER
DEVICE INPUT MODULE MODULE
NUMBER
OUTPUT OUTPUT
SIGNAL INPUT SIGNAL BLOCK
SIGNAL SIGNAL
PZ, ZQW PZ, ZQW
50, M12-P4.7 TB0CLK TBCLK
ACLK ACLK
Timer NA NA
SMCLK SMCLK
50, M12-P4.7 TB0CLK TBCLK
43, J8-P4.0 TB0.0 CCI0A 43, J8-P4.0
ADC12 (internal)
43, J8-P4.0 TB0.0 CCI0B
ADC12SHSx = {2}
CCR0 TB0 TB0.0
DV
SS
GND
DV
CC
V
CC
44, M9-P4.1 TB0.1 CCI1A 44, M9-P4.1
ADC12 (internal)
44, M9-P4.1 TB0.1 CCI1B
ADC12SHSx = {3}
CCR1 TB1 TB0.1
DV
SS
GND
DV
CC
V
CC
45, L9-P4.2 TB0.2 CCI2A 45, L9-P4.2
45, L9-P4.2 TB0.2 CCI2B
CCR2 TB2 TB0.2
DV
SS
GND
DV
CC
V
CC
46, L10-P4.3 TB0.3 CCI3A 46, L10-P4.3
46, L10-P4.3 TB0.3 CCI3B
CCR3 TB3 TB0.3
DV
SS
GND
DV
CC
V
CC
47, M10-P4.4 TB0.4 CCI4A 47, M10-P4.4
47, M10-P4.4 TB0.4 CCI4B
CCR4 TB4 TB0.4
DV
SS
GND
DV
CC
V
CC
48, L11-P4.5 TB0.5 CCI5A 48, L11-P4.5
48, L11-P4.5 TB0.5 CCI5B
CCR5 TB5 TB0.5
DV
SS
GND
DV
CC
V
CC
49, M11-P4.6 TB0.6 CCI6A 49, M11-P4.6
ACLK (internal) CCI6B
CCR6 TB6 TB0.6
DV
SS
GND
DV
CC
V
CC
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