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MSP430BT5190

www.ti.com

SLAS703A –APRIL 2010–REVISED AUGUST 2013

Mixed Signal Microcontroller

Check for Samples: MSP430BT5190

FEATURES

234

• Designed for Use With CC2560 TI Bluetooth ®

• Flexible Power Management System

Based Solutions

(1)

– Fully Integrated LDO With Programmable

• Commercially Licensed Mindtree™ Ethermind Regulated Core Supply Voltage

Bluetooth Stack for MSP430

– Supply Voltage Supervision, Monitoring,

– Bluetooth v2.1 + Enhanced Data Rate (EDR) and Brownout

Compliant

• Unified Clock System

– Serial Port Profile (SPP)

– FLL Control Loop for Frequency

– Sample Applications Stabilization

• Low Supply Voltage Range: – Low-Power Low-Frequency Internal Clock

3.6 V Down to 1.8 V Source (VLO)

• Ultralow-Power Consumption – Low-Frequency Trimmed Internal Reference

Source (REFO)

– Active Mode (AM):

All System Clocks Active – 32-kHz Crystals

230 µA/MHz at 8 MHz, 3 V, Flash Program

– High-Frequency Crystals up to 32 MHz

Execution (Typical)

• 16-Bit Timer TA0, Timer_A With Five

110 µA/MHz at 8 MHz, 3 V, RAM Program

Capture/Compare Registers

Execution (Typical)

• 16-Bit Timer TA1, Timer_A With Three

– Standby Mode (LPM3):

Capture/Compare Registers

Real-Time Clock With Crystal, Watchdog,

• 16-Bit Timer TB0, Timer_B With Seven

and Supply Supervisor Operational, Full

Capture/Compare Shadow Registers

RAM Retention, Fast Wake-Up:

• Up to Four Universal Serial Communication

1.7 µA at 2.2 V, 2.1 µA at 3 V (Typical)

Interfaces

Low-Power Oscillator (VLO), General-

Purpose Counter, Watchdog, and Supply – USCI_A0, USCI_A1, USCI_A2, and USCI_A3

Supervisor Operational, Full RAM Each Support:

Retention, Fast Wake-Up:

– Enhanced UART Supports Auto-

1.2 µA at 3 V (Typical)

Baudrate Detection

– Off Mode (LPM4):

– IrDA Encoder and Decoder

Full RAM Retention, Supply Supervisor

– Synchronous SPI

Operational, Fast Wake-Up:

– USCI_B0, USCI_B1, USCI_B2, and USCI_B3

1.2 µA at 3 V (Typical)

Each Support:

– Shutdown Mode (LPM4.5):

– I

0.1 µA at 3 V (Typical)

– Synchronous SPI

• Wake Up From Standby Mode in Less Than

• 12-Bit Analog-to-Digital Converter (ADC)

5 µs

– Internal Reference

• 16-Bit RISC Architecture

– 14 External Channels, 2 Internal Channels

• Hardware Multiplier Supports 32-Bit

Operations

• Serial Onboard Programming, No External

(1) The Bluetooth word mark and logos are owned by Bluetooth

Programming Voltage Needed

SIG, Inc., and any use of such marks by Texas Instruments is

under license.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2MSP430, Code Composer Studio are trademarks of Texas Instruments.

3Mindtree is a trademark of Mindtree Ltd.

4All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (101 pages)

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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Mixed Signal Microcontroller Check for Samples: MSP430BT5190 FEATURES 1 • Designed for Use With CC2560 TI Bluetooth ® Based Solutions (1) • Commercially Licensed Mindtree™ Ethermind Bluetooth Stack for MSP430 – Bluetooth v2.1 + Enhanced Data Rate (EDR) Compliant – Serial Port Profile (SPP) – Sample Applications • Low Supply Voltage Range: 3.6 V Down to 1.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 • • • • www.ti.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Functional Block Diagram XIN XOUT DVCC DVSS AVCC AVSS RST/NMI P1.x XT2IN XT2OUT Unified Clock System ACLK SMCLK 256KB 16KB Flash RAM MCLK CPUXV2 and Working Registers Power Management SYS LDO SVM/SVS Brownout Watchdog PA P2.x I/O Ports P1/P2 2×8 I/Os Interrupt Capability PA 1×16 I/Os P3.x PB P4.x P5.x PC P6.x P7.x PD P8.x PE P9.x P10.x PF P11.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com Pin Designation, MSP430BT5190IPZ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 MSP430BT5190IPZ P9.7 P9.6 P9.5/UCA2RXDUCA2SOMI P9.4/UCA2TXD/UCA2SIMO P9.3/UCB2CLK/UCA2STE P9.2/UCB2SOMI/UCB2SCL P9.1/UCB2SIMO/UCB2SDA P9.0/UCB2STE/UCA2CLK P8.7 P8.6/TA1.1 P8.5/TA1.0 DVCC2 DVSS2 VCORE P8.4/TA0.4 P8.3/TA0.3 P8.2/TA0.2 P8.1/TA0.1 P8.0/TA0.0 P7.3/TA1.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com Table 2. Terminal Functions TERMINAL NAME I/O (1) NO. DESCRIPTION PZ ZQW P6.4/A4 1 A1 I/O General-purpose digital I/O Analog input A4 – ADC P6.5/A5 2 E4 I/O General-purpose digital I/O Analog input A5 – ADC P6.6/A6 3 B1 I/O General-purpose digital I/O Analog input A6 – ADC P6.7/A7 4 C2 I/O General-purpose digital I/O Analog input A7 – ADC P7.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Table 2. Terminal Functions (continued) TERMINAL NAME I/O (1) NO. DESCRIPTION PZ ZQW P2.1/TA1.0 26 L2 I/O General-purpose digital I/O with port interrupt TA1 CCR0 capture: CCI0A input, compare: Out0 output P2.2/TA1.1 27 M2 I/O General-purpose digital I/O with port interrupt TA1 CCR1 capture: CCI1A input, compare: Out1 output P2.3/TA1.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com Table 2. Terminal Functions (continued) TERMINAL NAME I/O (1) NO. DESCRIPTION PZ ZQW P4.6/TB0.6 49 M11 I/O General-purpose digital I/O TB0 capture CCR6: CCI6A/CCI6B input, compare: Out6 output P4.7/TB0CLK/SMCLK 50 M12 I/O General-purpose digital I/O TB0 clock input SMCLK output P5.4/UCB1SOMI/UCB1SCL 51 L12 I/O General-purpose digital I/O Slave out, master in – USCI_B1 SPI mode I2C clock – USCI_B1 I2C mode P5.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Table 2. Terminal Functions (continued) TERMINAL NAME I/O (1) NO. DESCRIPTION PZ ZQW P9.3/UCB2CLK/UCA2STE 71 E9 I/O General-purpose digital I/O Clock signal input – USCI_B2 SPI slave mode Clock signal output – USCI_B2 SPI master mode Slave transmit enable – USCI_A2 SPI mode P9.4/UCA2TXD/UCA2SIMO 72 C11 I/O General-purpose digital I/O Transmit data – USCI_A2 UART mode Slave in, master out – USCI_A2 SPI mode P9.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com Table 2. Terminal Functions (continued) TERMINAL NAME I/O (1) NO. DESCRIPTION PZ ZQW (4) 94 D5 I/O General-purpose digital I/O JTAG test mode select PJ.3/TCK (4) 95 B4 I/O General-purpose digital I/O JTAG test clock RST/NMI/SBWTDIO (3) 96 A3 I/O Reset input active low (5) Non-maskable interrupt input Spy-Bi-Wire data input/output when Spy-Bi-Wire operation activated. P6.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Development Tools Support All MSP430™ microcontrollers are supported by a wide variety of software and hardware development tools. Tools are available from TI and various third parties. See them all at www.ti.com/msp430tools. Hardware Features See the Code Composer Studio for MSP430 User's Guide (SLAU157) for details on the available features.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.
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MSP430BT5190 www.ti.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com Short-Form Description CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Interrupt Vector Addresses The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 3.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Bootstrap Loader (BSL) The BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the device memory via the BSL is protected by an user-defined password. Usage of the BSL requires four pins as shown in Table 4. BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com Spy-Bi-Wire Interface In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface. SpyBi-Wire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire interface pin requirements are shown in Table 6. For further details on interfacing to development tools and device programmers, see the MSP430(tm) Hardware Tools User's Guide (SLAU278).
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). Digital I/O There are up to ten 8-bit I/O ports implemented: For 100-pin options, P1 through P10 are complete. P11 contains three individual I/O ports. For 80-pin options, P1 through P7 are complete.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com Real-Time Clock (RTC_A) The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated realtime clock (RTC) (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 System Module (SYS) The SYS module handles many of the system functions within the device. These include power on reset and power up clear handling, NMI source selection and management, reset interrupt vector generators, boot strap loader entry mechanisms, as well as, configuration management (device descriptors). It also includes a data exchange mechanism via JTAG called a JTAG mailbox that can be used in the application. Table 7.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com DMA Controller The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC12_A conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Universal Serial Communication Interface (USCI) The USCI modules are used for serial data communication. The USCI module supports synchronous communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as UART, enhanced UART with automatic baudrate detection, and IrDA. Each USCI module contains two portions, A and B.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com TA1 TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It can support multiple capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 10.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 TB0 TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. It can support multiple capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 11.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com ADC12_A The ADC12_A module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The conversionand-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Peripheral File Map Table 12.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com Table 13. Special Function Registers (Base Address: 0100h) REGISTER DESCRIPTION REGISTER OFFSET SFR interrupt enable SFRIE1 00h SFR interrupt flag SFRIFG1 02h SFR reset pin control SFRRPCR 04h Table 14.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Table 20.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com Table 23.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Table 26.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com Table 29.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Table 31.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com Table 33.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Table 34.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com Table 36.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Table 38.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com Table 41.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Table 43.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) Voltage applied at VCC to VSS –0.3 V to 4.1 V Voltage applied to any pin (excluding VCORE) (2) –0.3 V to VCC + 0.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 25 System Frequency - MHz 3 20 2 2, 3 1 1, 2 1, 2, 3 0, 1 0, 1, 2 0, 1, 2, 3 12 8 0 0 1.8 2.0 2.2 2.4 3.6 Supply Voltage - V The numbers within the fields denote the supported PMMCOREVx settings. Figure 2.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com Electrical Characteristics Active Mode Supply Current Into VCC Excluding External Current over recommended operating free-air temperature (unless otherwise noted) (1) (2) (3) FREQUENCY (fDCO = fMCLK = fSMCLK) PARAMETER IAM, IAM, (1) (2) (3) 42 Flash RAM EXECUTION MEMORY Flash RAM VCC 3V 3V PMMCOREVx 1 MHz 8 MHz 12 MHz TYP MAX TYP MAX 0 0.29 0.33 1.84 2.08 1 0.32 2.08 3.10 2 0.33 2.24 3.50 6.37 3 0.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Low-Power Mode Supply Currents (Into VCC) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER VCC PMMCOREVx -40°C TYP 25°C MAX TYP 60°C MAX TYP (2) 85°C MAX TYP MAX ILPM0,1MHz Low-power mode 0 (3) (4) 2.2 V 0 69 93 69 93 69 93 69 93 3V 3 73 100 73 100 73 100 73 100 ILPM2 Low-power mode 2 (5) (4) 2.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Outputs – General Purpose I/O (Full Drive Strength) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS I(OHmax) = –3 mA VOH I(OHmax) = –10 mA (2) High-level output voltage I(OHmax) = –5 mA (1) I(OHmax) = –15 mA (2) I(OLmax) = 3 mA VOL (2) 3V MAX VCC – 0.25 VCC VCC – 0.60 VCC VCC – 0.25 VCC VCC – 0.60 VCC VSS VSS + 0.25 VSS VSS + 0.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 8.0 VCC = 3.0 V Px.y IOL – Typical Low-Level Output Current – mA IOL – Typical Low-Level Output Current – mA 25.0 TA = 25°C 20.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TA = 25°C VCC = 3.0 V Px.y 55.0 50.0 IOL – Typical Low-Level Output Current – mA IOL – Typical Low-Level Output Current – mA 60.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com Crystal Oscillator, XT1, Low-Frequency Mode (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1, TA = 25°C ΔIDVCC.LF Differential XT1 oscillator crystal current consumption from lowest drive setting, LF mode fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 2, TA = 25°C 0.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Crystal Oscillator, XT1, High-Frequency Mode (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER IDVCC.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com DCO Frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT fDCO(0,0) DCO frequency (0, 0) DCORSELx = 0, DCOx = 0, MODx = 0 0.07 0.20 MHz fDCO(0,31) DCO frequency (0, 31) (1) DCORSELx = 0, DCOx = 31, MODx = 0 0.70 1.70 MHz fDCO(1,0) DCO frequency (1, 0) (1) DCORSELx = 1, DCOx = 0, MODx = 0 0.15 0.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 PMM, Brown-Out Reset (BOR) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS V(DVCC_BOR_IT–) BORH on voltage, DVCC falling level | dDVCC/dt | < 3 V/s V(DVCC_BOR_IT+) BORH off voltage, DVCC rising level | dDVCC/dt | < 3 V/s V(DVCC_BOR_hys) BORH hysteresis tRESET Pulse duration required at RST/NMI pin to accept a reset MIN 0.80 TYP 1.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com PMM, SVS High Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN SVSHE = 0, DVCC = 3.6 V I(SVSH) SVS current consumption V(SVSH_IT–) V(SVSH_IT+) tpd(SVSH) t(SVSH) 54 SVSH off voltage level (1) SVSH propagation delay SVSH on or off delay time dVDVCC/dt (1) SVSH on voltage level (1) TYP MAX 0 UNIT nA SVSHE = 1, DVCC = 3.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 PMM, SVM High Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN SVMHE = 0, DVCC = 3.6 V I(SVMH) V(SVMH) SVMH current consumption SVMH on or off voltage level (1) t(SVMH) (1) SVMH propagation delay SVMH on or off delay time MAX 0 UNIT nA SVMHE= 1, DVCC = 3.6 V, SVMHFP = 0 200 nA SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1 1.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com PMM, SVS Low Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP SVSLE = 0, PMMCOREV = 2 I(SVSL) SVSL current consumption tpd(SVSL) t(SVSL) SVSL propagation delay SVSL on or off delay time MAX UNIT 0 nA SVSLE = 1, PMMCOREV = 2, SVSLFP = 0 200 nA SVSLE = 1, PMMCOREV = 2, SVSLFP = 1 1.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Timer_A over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC fTA Timer_A input clock frequency Internal: SMCLK, ACLK External: TACLK Duty cycle = 50% ± 10% 1.8 V, 3 V tTA,cap Timer_A capture timing All capture inputs, Minimum pulse duration required for capture 1.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tHD,MO tVALID,MO SIMO Figure 12. SPI Master Mode, CKPH = 0 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tHD,MO tVALID,MO SIMO Figure 13.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tSU,SI tLO/HI tHD,SI SIMO tHD,SO tVALID,SO tSTE,ACC tSTE,DIS SOMI Figure 14. SPI Slave Mode, CKPH = 0 tSTE,LAG tSTE,LEAD STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tHD,SI tSU,SI SIMO tSTE,ACC tHD,MO tVALID,SO tSTE,DIS SOMI Figure 15.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com USCI (I2C Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 16) PARAMETER TEST CONDITIONS VCC MIN TYP Internal: SMCLK, ACLK External: UCLK Duty cycle = 50% ± 10% MAX UNIT fSYSTEM MHz 400 kHz fUSCI USCI input clock frequency fSCL SCL clock frequency tHD,STA Hold time (repeated) START tSU,STA Setup time for a repeated START tHD,DAT Data hold time 2.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 REF, External Reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TEST CONDITIONS (2) VCC MIN TYP MAX UNIT VeREF+ Positive external reference voltage input VeREF+ > VREF–/VeREF– 1.4 AVCC V VREF–/VeREF– Negative external reference voltage input VeREF+ > VREF–/VeREF– (3) 0 1.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 JTAG and Spy-Bi-Wire Interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSBW Spy-Bi-Wire input frequency 2.2 V, 3 V 0 20 MHz tSBW,Low Spy-Bi-Wire low clock pulse length 2.2 V, 3 V 0.025 15 µs tSBW, En Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge) (1) 2.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com INPUT/OUTPUT SCHEMATICS Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger Pad Logic P1REN.x P1DIR.x 0 0 Module X OUT 1 0 DVCC 1 P1DS.x 0: Low drive 1: High drive P1SEL.x P1IN.x EN Module X IN 1 Direction 0: Input 1: Output 1 P1OUT.x DVSS P1.0/TA0CLK/ACLK P1.1/TA0.0 P1.2/TA0.1 P1.3/TA0.2 P1.4/TA0.3 P1.5/TA0.4 P1.6/SMCLK P1.7 D P1IE.x EN P1IRQ.x Q P1IFG.x P1SEL.x P1IES.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Table 44. Port P1 (P1.0 to P1.7) Pin Functions PIN NAME (P1.x) P1.0/TA0CLK/ACLK P1.1/TA0.0 P1.2/TA0.1 P1.3/TA0.2 P1.4/TA0.3 x 0 1 2 3 4 FUNCTION P1.0 (I/O) 0 0 1 ACLK 1 1 I: 0; O: 1 0 TA0.CCI0A 0 1 TA0.0 1 1 I: 0; O: 1 0 TA0.CCI1A 0 1 TA0.1 1 1 I: 0; O: 1 0 TA0.CCI2A 0 1 TA0.2 1 1 I: 0; O: 1 0 0 1 P1.1 (I/O) P1.2 (I/O) P1.3 (I/O) P1.4 (I/O) P1.5 (I/O) TA0.CCI4A TA0.4 P1.6/SMCLK 6 P1.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger Pad Logic P2REN.x P2DIR.x 0 0 Module X OUT 1 0 DVCC 1 P2DS.x 0: Low drive 1: High drive P2SEL.x P2IN.x EN Module X IN 1 Direction 0: Input 1: Output 1 P2OUT.x DVSS P2.0/TA1CLK/MCLK P2.1/TA1.0 P2.2/TA1.1 P2.3/TA1.2 P2.4/RTCCLK P2.5 P2.6/ACLK P2.7/ADC12CLK/DMAE0 D P2IE.x EN P2IRQ.x Q P2IFG.x P2SEL.x P2IES.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Table 45. Port P2 (P2.0 to P2.7) Pin Functions PIN NAME (P2.x) P2.0/TA1CLK/MCLK P2.1/TA1.0 P2.2/TA1.1 P2.3/TA1.2 P2.4/RTCCLK x 0 1 2 3 4 FUNCTION CONTROL BITS/SIGNALS P2DIR.x P2SEL.x P2.0 (I/O) I: 0; O: 1 0 TA1CLK 0 1 MCLK 1 1 I: 0; O: 1 0 TA1.CCI0A 0 1 TA1.0 1 1 I: 0; O: 1 0 TA1.CCI1A 0 1 TA1.1 1 1 I: 0; O: 1 0 TA1.CCI2A 0 1 TA1.2 1 1 P2.4 (I/O) I: 0; O: 1 0 RTCCLK 1 1 P2.1 (I/O) P2.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger Pad Logic P3REN.x P3DIR.x 0 0 Module X OUT 1 0 DVCC 1 P3DS.x 0: Low drive 1: High drive P3SEL.x P3IN.x EN Module X IN 1 Direction 0: Input 1: Output 1 P3OUT.x DVSS P3.0/UB0STE/UCA0CLK P3.1/UCB0SIMO/UCB0SDA P3.2/UCB0SOMI/UCB0SCL P3.3/USC0CLK/UCA0STE P3.4/UCA0TXD/UCA0SIMO P3.5/UCA0RXD/UCA0SOMI P3.6/UCB1STE/UCA1CLK P3.7/UCB1SIMO/UCB1SDA D Table 46. Port P3 (P3.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger Pad Logic P4REN.x P4DIR.x 0 0 Module X OUT 1 0 DVCC 1 P4DS.x 0: Low drive 1: High drive P4SEL.x P4IN.x EN Module X IN 1 Direction 0: Input 1: Output 1 P4OUT.x DVSS P4.0/TB0.0 P4.1/TB0.1 P4.2/TB0.2 P4.3/TB0.3 P4.4/TB0.4 P4.5/TB0.5 P4.6/TB0.6 P4.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com Table 47. Port P4 (P4.0 to P4.7) Pin Functions PIN NAME (P4.x) P4.0/TB0.0 P4.1/TB0.1 P4.2/TB0.2 P4.3/TB0.3 P4.4/TB0.5 x 0 1 2 3 4 FUNCTION 4.0 (I/O) 0 0 1 TB0.0 (1) 1 1 4.1 (I/O) I: 0; O: 1 0 TB0.CCI1A and TB0.CCI1B 0 1 TB0.1 (1) 1 1 4.2 (I/O) I: 0; O: 1 0 TB0.CCI2A and TB0.CCI2B 0 1 TB0.2 (1) 1 1 4.3 (I/O) I: 0; O: 1 0 TB0.CCI3A and TB0.CCI3B 0 1 TB0.3 (1) 1 1 4.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger Pad Logic To ADC12 INCHx = y To/From ADC12 Reference P5REN.x P5DIR.x DVSS 0 DVCC 1 1 0 1 P5OUT.x 0 Module X OUT 1 P5DS.x 0: Low drive 1: High drive P5SEL.x P5.0/A8/VREF+/VeREF+ P5.1/A9/VREF–/VeREF– P5IN.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com Table 48. Port P5 (P5.0 and P5.1) Pin Functions PIN NAME (P5.x) P5.0/A8/VREF+/VeREF+ P5.1/A9/VREF–/VeREF– (1) (2) (3) (4) (5) (6) 76 x 0 1 FUNCTION P5.0 (I/O) (2) CONTROL BITS/SIGNALS (1) P5DIR.x P5SEL.x REFOUT I: 0; O: 1 0 X A8/VeREF+ (3) X 1 0 A8/VREF+ (4) X 1 1 P5.1 (I/O) (2) I: 0; O: 1 0 X A9/VeREF– (5) X 1 0 A9/VREF– (6) X 1 1 X = Don't care Default condition Setting the P5SEL.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Port P5, P5.2, Input/Output With Schmitt Trigger Pad Logic To XT2 P5REN.2 P5DIR.2 DVSS 0 DVCC 1 1 0 1 P5OUT.2 0 Module X OUT 1 P5DS.2 0: Low drive 1: High drive P5SEL.2 P5.2/XT2IN P5IN.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com Port P5, P5.3, Input/Output With Schmitt Trigger Pad Logic To XT2 P5REN.3 P5DIR.3 DVSS 0 DVCC 1 1 0 1 P5OUT.3 0 Module X OUT 1 P5.3/XT2OUT P5DS.3 0: Low drive 1: High drive P5SEL.3 P5IN.3 Bus Keeper EN Module X IN D Table 49. Port P5 (P5.2) Pin Functions PIN NAME (P5.x) P5.2/XT2IN P5.3/XT2OUT (1) (2) (3) 78 x 2 3 FUNCTION P5.2 (I/O) CONTROL BITS/SIGNALS (1) P5DIR.x P5SEL.2 P5SEL.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Port P5, P5.4 to P5.7, Input/Output With Schmitt Trigger Pad Logic P5REN.x P5DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P5OUT.x DVSS P5.4/UCB1SOMI/UCB1SCL P5.5/UCB1CLK/UCA1STE P5.6/UCA1TXD/UCA1SIMO P5.7/UCA1RXD/UCA1SOMI P5DS.x 0: Low drive 1: High drive P5SEL.x P5IN.x EN Module X IN D Table 50. Port P5 (P5.4 to P5.7) Pin Functions PIN NAME (P5.x) x P5.4/UCB1SOMI/UCB1SCL 4 FUNCTION P5.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger Pad Logic To ADC12 INCHx = y P6REN.x P6DIR.x DVSS 0 DVCC 1 1 0 1 P6OUT.x 0 Module X OUT 1 P6DS.x 0: Low drive 1: High drive P6SEL.x P6IN.x EN Module X IN 80 Bus Keeper P6.0/A0 P6.1/A1 P6.2/A2 P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6 P6.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Table 51. Port P6 (P6.0 to P6.7) Pin Functions PIN NAME (P6.x) P6.0/A0 x 0 FUNCTION P6.0 (I/O) A0 (2) P6.1/A1 1 P6.1 (I/O) A1 (2) P6.2/A2 2 3 4 5 6 7 (3) (3) P6.7 (I/O) A7 (2) (1) (2) (2) (3) P6.6 (I/O) A6 (2) P6.7/A7 (3) P6.5 (I/O) A5 (1) P6.6/A6 (3) P6.4 (I/O) A4 (2) P6.5/A5 (3) P6.3 (I/O) A3 (2) P6.4/A4 (3) P6.2 (I/O) A2 (2) P6.3/A3 (3) (3) CONTROL BITS/SIGNALS (1) P6DIR.x P6SEL.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com Port P7, P7.0, Input/Output With Schmitt Trigger Pad Logic To XT1 P7REN.0 P7DIR.0 DVSS 0 DVCC 1 1 0 1 P7OUT.0 0 Module X OUT 1 P7DS.0 0: Low drive 1: High drive P7SEL.0 P7.0/XIN P7IN.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Port P7, P7.1, Input/Output With Schmitt Trigger Pad Logic To XT1 P7REN.1 P7DIR.1 DVSS 0 DVCC 1 1 0 1 P7OUT.1 0 Module X OUT 1 P7.1/XOUT P7DS.1 0: Low drive 1: High drive P7SEL.0 XT1BYPASS P7IN.1 Bus Keeper EN Module X IN D Table 52. Port P7 (P7.0 and P7.1) Pin Functions PIN NAME (P7.x) P7.0/XIN x 0 FUNCTION P7.0 (I/O) XIN crystal mode (2) XIN bypass mode P7.1/XOUT 1 (3) P7DIR.x P7SEL.0 P7SEL.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com Port P7, P7.2 and P7.3, Input/Output With Schmitt Trigger Pad Logic P7REN.x P7DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P7OUT.x DVSS P7.2/TB0OUTH/SVMOUT P7.3/TA1.2 P7DS.x 0: Low drive 1: High drive P7SEL.x P7IN.x EN Module X IN D Table 53. Port P7 (P7.2 and P7.3) Pin Functions PIN NAME (P7.x) P7.2/TB0OUTH/SVMOUT P7.3/TA1.2 84 x 2 3 FUNCTION CONTROL BITS/SIGNALS P7DIR.x P7SEL.x P7.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger Pad Logic To ADC12 INCHx = y P7REN.x P7DIR.x DVSS 0 DVCC 1 1 0 1 P7OUT.x 0 Module X OUT 1 P7.4/A12 P7.5/A13 P7.6/A14 P7.7/A15 P7DS.x 0: Low drive 1: High drive P7SEL.x P7IN.x Bus Keeper EN D Module X IN Table 54. Port P7 (P7.4 to P7.7) Pin Functions PIN NAME (P7.x) P7.4/A12 x 4 FUNCTION P7.4 (I/O) A12 (2) P7.5/A13 5 P7.5 (I/O) A13 (4) P7.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger Pad Logic P8REN.x P8DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P8OUT.x DVSS P8.0/TA0.0 P8.1/TA0.1 P8.2/TA0.2 P8.3/TA0.3 P8.4/TA0.4 P8.5/TA1.0 P8.6/TA1.1 P8.7 P8DS.x 0: Low drive 1: High drive P8SEL.x P8IN.x EN D Module X IN Table 55. Port P8 (P8.0 to P8.7) Pin Functions PIN NAME (P8.x) P8.0/TA0.0 P8.1/TA0.1 P8.2/TA0.2 P8.3/TA0.3 P8.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger Pad Logic P9REN.x P9DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P9OUT.x DVSS P9.0/UCB2STE/UCA2CLK P9.1/UCB2SIMO/UCB2SDA P9.2/UCB2SOMI/UCB2SCL P9.3/UCB2CLK/UCA2STE P9.4/UCA2TXD/UCA2SIMO P9.5/UCA2RXD/UCA2SOMI P9.6 P9.7 P9DS.x 0: Low drive 1: High drive P9SEL.x P9IN.x EN Module X IN D Table 56. Port P9 (P9.0 to P9.7) Pin Functions PIN NAME (P9.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com Port P10, P10.0 to P10.7, Input/Output With Schmitt Trigger Pad Logic P10REN.x P10DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P10OUT.x DVSS P10DS.x 0: Low drive 1: High drive P10SEL.x P10IN.x EN Module X IN P10.0/UCB3STE/UCA3CLK P10.1/UCB3SIMO/UCB3SDA P10.2/UCB3SOMI/UCB3SCL P10.3/UCB3CLK/UCA3STE P10.4/UCA3TXD/UCA3SIMO P10.5/UCA3RXD/UCA3SOMI P10.6 P10.7 D Table 57. Port P10 (P10.0 to P10.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Port P11, P11.0 to P11.2, Input/Output With Schmitt Trigger Pad Logic P11REN.x P11DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P11OUT.x DVSS P11.0/ACLK P11.1/MCLK P11.2/SMCLK P11DS.x 0: Low drive 1: High drive P11SEL.x P11IN.x EN D Module X IN Table 58. Port P11 (P11.0 to P11.2) Pin Functions PIN NAME (P11.x) P11.0/ACLK x 0 FUNCTION P11.0 (I/O) ACLK P11.1/MCLK 1 P11.2/SMCLK 2 P11.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com Port J, J.0 JTAG pin TDO, Input/Output With Schmitt Trigger or Output Pad Logic PJREN.0 PJDIR.0 0 DVCC 1 PJOUT.0 0 From JTAG 1 DVSS 0 DVCC 1 1 PJ.0/TDO PJDS.0 0: Low drive 1: High drive From JTAG PJIN.0 EN D Port J, J.1 to J.3 JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output Pad Logic PJREN.x PJDIR.x 0 DVSS 1 PJOUT.x 0 From JTAG 1 DVSS 0 DVCC 1 PJDS.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Table 59. Port PJ (PJ.0 to PJ.3) Pin Functions PIN NAME (PJ.x) x CONTROL BITS/ SIGNALS (1) FUNCTION PJDIR.x PJ.0/TDO 0 (2) I: 0; O: 1 PJ.1 (I/O) (2) I: 0; O: 1 PJ.0 (I/O) TDO (3) PJ.1/TDI/TCLK 1 X TDI/TCLK (3) PJ.2/TMS 2 PJ.2 (I/O) TMS (3) PJ.3/TCK 3 (1) (2) (3) (4) X I: 0; O: 1 (4) PJ.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com DEVICE DESCRIPTORS (TLV) Table 60 shows the complete contents of the device descriptor tag-length-value (TLV) structure. Table 60.
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 Table 60.
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MSP430BT5190 SLAS703A – APRIL 2010 – REVISED AUGUST 2013 www.ti.com Table 60. Device Descriptor Table(1) (continued) Description Interrupts 94 Address Size bytes MSP430BT5190 Value MPY32 2 02h 85h DMA-3 2 04h 47h USCI_A/B 2 0Ch 90h USCI_A/B 2 04h 90h USCI_A/B 2 04h 90h USCI_A/B 2 04h 90h ADC12_A 2 08h D1h TB0.CCIFG0 1 64h TB0.CCIFG1..6 1 65h WDTIFG 1 40h USCI_A0 1 90h USCI_B0 1 91h ADC12_A 1 D0h TA0.CCIFG0 1 60h TA0.CCIFG1..
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MSP430BT5190 www.ti.com SLAS703A – APRIL 2010 – REVISED AUGUST 2013 REVISION HISTORY REVISION DESCRIPTION SLAS703 Product Preview release SLAS703A Added Applications, Development Tools Support, and Device and Development Tool Nomenclature. Table 2, Added note about pullup resistor to RST/NMI/SBWTDIO pin. Table 7, Changed SYSRSTIV interrupt event at 1Ch to Reserved.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 10-Nov-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device MSP430BT5190IPZR Package Package Pins Type Drawing LQFP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PZ 100 1000 330.0 24.4 17.0 17.0 2.1 20.0 24.0 Q2 MSP430BT5190IZQWR BGA MI CROSTA R JUNI OR ZQW 113 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1 MSP430BT5190IZQWT BGA MI CROSTA R JUNI OR ZQW 113 250 330.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 10-Nov-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430BT5190IPZR LQFP PZ 100 1000 367.0 367.0 45.0 MSP430BT5190IZQWR BGA MICROSTAR JUNIOR ZQW 113 2500 336.6 336.6 28.6 MSP430BT5190IZQWT BGA MICROSTAR JUNIOR ZQW 113 250 336.6 336.6 28.
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MECHANICAL DATA MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996 PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 75 0,08 M 51 76 50 100 26 1 0,13 NOM 25 12,00 TYP Gage Plane 14,20 SQ 13,80 16,20 SQ 15,80 0,05 MIN 1,45 1,35 0,25 0°– 7° 0,75 0,45 Seating Plane 0,08 1,60 MAX 4040149 /B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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