Datasheet

MSP430C11x1, MSP430F11x1A
MIXED SIGNAL MICROCONTROLLER
SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Schmitt-trigger inputs − Ports P1 (P1.0 to P1.7) and P2 (P2.0 to P2.5)
PARAMETER V
CC
MIN TYP MAX UNIT
V
Positive going input threshold voltage
2.2 V 1.1 1.5
V
V
IT+
Positive-going input threshold voltage
3 V
1.5 1.9
V
V
Negative going input threshold voltage
2.2 V 0.4 0.9
V
V
IT−
Negative-going input threshold voltage
3 V
0.9 1.3
V
V
Input voltage hysteresis (V V )
2.2 V 0.3 1.1
V
V
hys
Input voltage hysteresis (V
IT+
− V
IT−
)
3 V 0.5 1
V
standard inputs − RST/NMI, JTAG (TCK, TMS, TDI/TCLK)
PARAMETER V
CC
MIN TYP MAX UNIT
V
IL
Low-level input voltage
22V/3V
V
SS
V
SS
+0.6 V
V
IH
High-level input voltage
2.2 V / 3 V
0.8×V
CC
V
CC
V
inputs Px.x, TAx
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
P t P1 P2 P1 t P2 E t l t i i l
2.2 V/3 V 1.5 cycle
t
(int)
External interrupt timing
Port P1, P2: P1.x to P2.x, External trigger signal
for the interrupt flag (see Note 1)
2.2 V 62
ns
(int)
pg
for
the
interrupt
flag
(see
Note
1)
3 V 50
ns
t
()
Timer A capture timing
TA0 TA1 TA2
2.2 V 62
ns
t
(cap)
Timer_A, capture timing TA0, TA1, TA2
3 V 50
ns
f
Timer_A clock frequenc
y
TACLK INCLK t =t
2.2 V 8
MHz
f
(TAext)
Timer
_
A
clock
frequency
externally applied to pin
TACLK, INCLK
t
(H)
= t
(L)
3 V 10
MHz
f
Timer A clock frequency
SMCLK or ACLK signal selected
2.2 V 8
MHz
f
(TAint)
Timer_A clock frequency SMCLK or ACLK signal selected
3 V 10
MHz
NOTES: 1. The external signal sets the interrupt flag every time the minimum t
(int)
cycle and time parameters are met. It may be set even with
trigger signals shorter than t
(int)
. Both the cycle and timing specifications must be met to ensure the flag is set. t
(int)
is measured in
MCLK cycles.
leakage current
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
I
High impedance leakage current
Port P1: P1.x, 0 ≤ ×≤ 7
(see Notes 1 and 2)
2.2 V/3 V ±50
nA
I
lkg(Px.x)
High-impedance leakage current
Port P2: P2.x, 0 ≤ ×≤ 5
(see Notes 1 and 2)
2.2 V/3 V ±50
nA
NOTES: 1. The leakage current is measured with V
SS
or V
CC
applied to the corresponding pin(s), unless otherwise noted.
2. The leakage of the digital port pins is measured individually. The port pin must be selected for input and there must be no optional
pullup or pulldown resistor.