Datasheet

MSP430C11x1, MSP430F11x1A
MIXED SIGNAL MICROCONTROLLER
SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
outputs − Ports P1 (P1.0 to P1.7) and P2 (P2.0 to P2.5)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
(OHmax)
= −1.5 mA
V 22V
See Note 1 V
CC
−0.25 V
CC
V
High-level output voltage
Port 1 and Port 2 (C11x1)
I
(OHmax)
= −6 mA
V
CC
= 2.2 V
See Note 2 V
CC
−0.6 V
CC
V
V
OH
Port 1 and Port 2 (C11x1)
P
o
rt 1
(
F11x1A
)
I
(OHmax)
= −1.5 mA
V 3V
See Note 1 V
CC
−0.25 V
CC
V
Port
1
(F11x1A)
I
(OHmax)
= −6 mA
V
CC
= 3 V
See Note 2 V
CC
−0.6 V
CC
I
(OHmax)
= −1 mA
V 22V
See Note 3 V
CC
−0.25 V
CC
V
Hi
g
h-level output volta
g
e
I
(OHmax)
= −3.4 mA
V
CC
= 2.2 V
See Note 3 V
CC
−0.6 V
CC
V
V
OH
High level
output
voltage
Port 2 (F11x1A)
I
(OHmax)
= −1 mA
V 3V
See Note 3 V
CC
−0.25 V
CC
V
I
(OHmax)
= −3.4 mA
V
CC
= 3 V
See Note 3 V
CC
−0.6 V
CC
I
(OLmax)
= 1.5 mA
V 22V
See Note 1 V
SS
V
SS
+0.25
V
Low-level output voltage
Port 1 and Port 2 (C11x1
I
(OLmax)
= 6 mA
V
CC
= 2.2 V
See Note 2 V
SS
V
SS
+0.6
V
V
OL
Port 1 and Port 2 (C11x1,
F11x1A
)
I
(OLmax)
= 1.5 mA
V =3V
See Note 1 V
SS
V
SS
+0.25
V
F11x1A)
I
(OLmax)
= 6 mA
V
CC
= 3 V
See Note 2 V
SS
V
SS
+0.6
NOTES: 1. The maximum total current, I
OHmax
and I
OLmax
, for all outputs combined, should not exceed ±12 mA to hold the maximum voltage
drop specified.
2. The maximum total current, I
OHmax
and I
OLmax
, for all outputs combined, should not exceed ±48 mA to hold the maximum voltage
drop specified.
3. One output loaded at a time.
output frequency
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
f
P20
P2.0/ACLK, C
L
= 20 pF 2.2 V/3 V f
System
f
TAx
Output frequency
TA0, TA1, TA2, C
L
= 20 pF
Internal clock source, SMCLK signal applied (see Note 1)
2.2 V/3 V dc f
System
MHz
f
SMCLK
= f
LFXT1
= f
XT1
40% 60%
P1 4/SMCLK
f
SMCLK
= f
LFXT1
= f
LF
2 2 V/3 V
35% 65%
P1.4/SMCLK,
C
L
= 20 pF
f
SMCLK
= f
LFXT1/n
2
.
2
V/3
V
50%−
15 ns
50%
50%+
15 ns
t
Xdc
Duty cycle of O/P
frequency
f
SMCLK
= f
DCOCLK
2.2 V/3 V
50%−
15 ns
50%
50%+
15 ns
frequency
P2 0/ACLK
f
P20
= f
LFXT1
= f
XT1
40% 60%
P2.0/ACLK,
C
L
=20pF
f
P20
= f
LFXT1
= f
LF
2.2 V/3 V
30% 70%
C
L
=
20
p
F
f
P20
= f
LFXT1/n
50%
t
TAdc
TA0, TA1, TA2, C
L
= 20 pF, duty cycle = 50% 2.2 V/3 V 0 ±50 ns
NOTE 1: The limits of the system clock MCLK has to be met. MCLK and SMCLK can have different frequencies.