Datasheet

MSP430C11x1, MSP430F11x1A
MIXED SIGNAL MICROCONTROLLER
SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
RGE PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
TEST
V
CC
P2.5/R
osc
V
SS
XOUT
XIN
RST
/NMI
P2.0/ACLK
P2.1/INCLK
P2.2/CAOUT/TA0
P1.7/TA2/TDO/TDI
P1.6/TA1/TDI/TCLK
P1.5/TA0/TMS
P1.4/SMCLK/TCK
P1.3/TA2
P1.2/TA1
P1.1/TA0
P1.0/TACLK
P2.4/CA1/TA2
P2.3/CA0/TA1
DW, PW, or DGV PACKAGE
(TOP VIEW)
V
SS
P2.5/R
OSC
XOUT
V
CC
XIN
TEST
RST/NMI
P1.7/TA2/TDO/TDI
P2.0/ACLK
P1.6/TA1/TDI/TCLK
NC
NC
P1.4/SMCLK/TCK
P1.3/TA2
P1.2/TA1
P1.1/TA0
P1.0/TACLK
P1.5/TA0/TMS
Note: NC pins not internally connected
P2.1/INCLK
P2.2/CAOUT/TA0
NC
P2.3/CA0/TA1 P2.4/CA1/TA2
NC
1
2
3
4
5
6
18
17
16
15
14
13
891011
20212223
Power Pad connection to V
SS
recommended
functional block diagram
Oscillator
ACLK
SMCLK
CPU
Incl. 16 Reg.
Bus
Conv
MCB
XIN XOUT P2
MDB, 16 Bit
MAB, 16 Bit
MCLK
MAB,
4 Bit
V
CC
V
SS
RST/NMI
System
Clock
R
OSC
P1/JTAG
Flash/ROM
4KB
2KB
1KB
RAM
256B
128B
128B
Watchdog
Timer
15/16-Bit
Timer_A3
3 CC Reg
I/O Port 1
8 I/Os, with
Interrupt
Capability
I/O Port 2
6 I/Os, with
Interrupt
Capability
POR
MDB, 16-Bit
MAB, 16-Bit
TEST
Test
JTAG
8 6
Comparator
A
MDB, 8 Bit
Emulation
Module
(F versions only)