Datasheet

MSP430C11x1, MSP430F11x1A
MIXED SIGNAL MICROCONTROLLER
SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
interrupt enable 1 and 2
7654 0
OFIE WDTIE
32 1
rw-0 rw-0 rw-0
Address
0h
NMIIEACCVIE
rw-0
WDTIE: Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer
is configured in interval timer mode.
OFIE: Oscillator fault enable
NMIIE: (Non)maskable interrupt enable
ACCVIE: Flash access violation interrupt enable
7654 032 1
Address
01h
interrupt flag register 1 and 2
7654 0
OFIFG WDTIFG
32 1
rw-0 rw-1 rw-(0)
Address
02h NMIIFG
WDTIFG: Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on V
CC
power up or a reset condition at RST/NMI pin in reset mode.
OFIFG: Flag set on oscillator fault
NMIIFG: Set via RST
/NMI pin
7654 032 1
Address
03h
Legend rw:
rw-0,1:
Bit can be read and written.
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
rw-(0,1):
SFR bit is not present in device