Datasheet

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  
SLAS361D − JANUARY 2002 − REVISED AUGUST 2004
38
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic (continued)
port P3, P3.3, input/output with Schmitt-trigger
P3.3/UCLK0
P3IN.3
Pad Logic
EN
D
P3OUT.3
P3DIR.3
P3SEL.3
UCLK.0
0
1
0
1
DCM_UCLK
SYNC
MM
STE
STC
From USART0
UCLK0
To USART0
0: Input
1: Output
NOTE: UART mode: The UART clock can only be an input. If UART mode and UART function are selected, the P3.3/UCLK0 is always
an input.
SPI, slave mode: The clock applied to UCLK0 is used to shift data in and out.
SPI, master mode: The clock to shift data in and out is supplied to connected devices on pin P3.3/UCLK0 (in slave mode).
port P3, P3.4, and P3.5 input/output with Schmitt-trigger
P3IN.x
Module X IN
Pad Logic
EN
D
P3OUT.x
P3DIR.x
P3SEL.x
Module X OUT
Direction Control
From Module
0
1
0
1
P3.4/UTXD0
P3.5/URXD0
0: Input
1: Output
x {4,5}
PnSel.x
PnDIR.x
DIRECTION
CONTROL
FROM MODULE
PnOUT.x MODULE X OUT PnIN.x MODULE X IN
P3Sel.4 P3DIR.4 V
CC
P3OUT.4 UTXD0
†
P3IN.4 Unused
P3Sel.5 P3DIR.5 V
SS
P3OUT.5 V
SS
P3IN.5 URXD0
‡
†
Output from USART0 module
‡
Input to USART0 module