MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 D Low Supply-Voltage Range: 1.8 V to 3.6 V D Ultralow Power Consumption D D D D D D D D D D D D D D − Active Mode: 330 μA at 1 MHz, 2.2 V − Standby Mode: 1.1 μA − Off Mode (RAM Retention): 0.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 description (continued) The MSP430F15x/16x/161x series are microcontroller configurations with two built-in 16-bit timers, a fast 12-bit A/D converter, dual 12-bit D/A converter, one or two universal serial synchronous/asynchronous communication interfaces (USART), I2C, DMA, and 48 I/O pins.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 pin designation, MSP430F155, MSP430F156, and MSP430F157 AVCC DVSS AVSS P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P5.7/TBOUTH/SVSOUT P5.6/ACLK P5.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 pin designation, MSP430F167, MSP430F168, MSP430F169 AVCC DVSS AVSS P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P5.7/TBOUTH/SVSOUT P5.6/ACLK P5.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 pin designation, MSP430F1610, MSP430F1611, MSP430F1612 AVCC DVSS AVSS P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P5.7/TBOUTH/SVSOUT P5.6/ACLK P5.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 functional block diagram, MSP430F15x XIN XOUT DVCC DVSS AVCC AVSS P1 RST/NMI P2 8 ROSC Oscillator XT2IN System Clock XT2OUT ACLK 32KB Flash 1KB RAM ADC12 DAC12 SMCLK 24KB Flash 1KB RAM 16KB Flash 512B RAM 12-Bit 8 Channels <10μs Conv.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 functional block diagram, MSP430F161x XIN XOUT DVCC DVSS AVCC AVSS P1 RST/NMI P2 8 ROSC Oscillator XT2IN System Clock XT2OUT ACLK 55KB Flash 5KB RAM ADC12 DAC12 SMCLK 48KB Flash 10KB RAM 32KB Flash 5KB RAM 12-Bit 8 Channels <10μs Conv.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION AVCC 64 Analog supply voltage, positive terminal. Supplies only the analog portion of ADC12 and DAC12. AVSS 62 Analog supply voltage, negative terminal. Supplies only the analog portion of ADC12 and DAC12. DVCC 1 Digital supply voltage, positive terminal. Supplies all digital parts. DVSS 63 P1.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 Terminal Functions (Continued) TERMINAL NAME NO. I/O DESCRIPTION P5.4/MCLK 48 I/O General-purpose digital I/O pin/main system clock MCLK output P5.5/SMCLK 49 I/O General-purpose digital I/O pin/submain system clock SMCLK output P5.6/ACLK 50 I/O General-purpose digital I/O pin/auxiliary clock ACLK output P5.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 short-form description CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 operating modes The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 interrupt vector addresses The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 special function registers Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits not allocated to a functional purpose are not physically present in the device. This arrangement provides simple software access.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 module enable registers 1 and 2 7 UTXE0 Address 04h rw-0 6 URXE0 USPIE0 5 3 USART0: UART mode receive enable UTXE0: USART0: UART mode transmit enable USPIE0: USART0: SPI mode transmit and receive enable 05h 7 6 5 UTXE1 rw-0 4 URXE1 USPIE1 3 rw-0 URXE1†: USART1: UART mode receive enable UTXE1†: USART1: UART mode transmit enable USPIE1†: USART1: SPI mode transmit and receive en
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 memory organization, MSP430F15x MSP430F155 MSP430F156 MSP430F157 Memory Main: interrupt vector Main: code memory Size Flash Flash 16KB 0FFFFh − 0FFE0h 0FFFFh − 0C000h 24KB 0FFFFh − 0FFE0h 0FFFFh − 0A000h 32KB 0FFFFh − 0FFE0h 0FFFFh − 08000h Information memory Size Flash 256 Byte 010FFh − 01000h 256 Byte 010FFh − 01000h 256 Byte 010FFh − 01000h Boot memory Size ROM 1KB 0FFFh − 0C00h
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 bootstrap loader (BSL) The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the Application report Features of the MSP430 Bootstrap Loader, Literature Number SLAA089.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 peripherals Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, see the MSP430x1xx Family User’s Guide, literature number SLAU049. DMA controller The DMA controller allows movement of data from one memory address to another without CPU intervention.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 USART0 The MSP430F15x and the MSP430F16x(x) have one hardware universal synchronous/asynchronous receive transmit (USART0) peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4 pin), asynchronous UART and I2C communication protocols using double-buffered transmit and receive channels.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 Timer_B7 (MSP430F16x/161x only) Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 Comparator_A The primary function of the comparator_A module is to support precision slope analog−to−digital conversions, battery−voltage supervision, and monitoring of external analog signals. ADC12 The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator and a 16 word conversion-and-control buffer.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 peripheral file map PERIPHERAL FILE MAP DMA DAC12 ADC12 DMA channel 2 transfer size DMA2SZ 01F6h DMA channel 2 destination address DMA2DA 01F4h DMA channel 2 source address DMA2SA 01F2h DMA channel 2 control DMA2CTL 01F0h DMA channel 1 transfer size DMA1SZ 01EEh DMA channel 1 destination address DMA1DA 01ECh DMA channel 1 source address DMA1SA 01EAh DMA channel 1 control DM
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 peripheral file map (continued) PERIPHERAL FILE MAP (CONTINUED) ADC12 (continued) Timer_B7/ _ Timer_B3 (see Note 1) Timer_A3 _ ADC memory-control register15 ADC12MCTL15 08Fh ADC memory-control register14 ADC12MCTL14 08Eh ADC memory-control register13 ADC12MCTL13 08Dh ADC memory-control register12 ADC12MCTL12 08Ch ADC memory-control register11 ADC12MCTL11 08Bh ADC memory-control re
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 peripheral file map (continued) PERIPHERAL FILE MAP (CONTINUED) Timer_A3 _ (continued) Capture/compare control 2 TACCTL2 0166h Capture/compare control 1 TACCTL1 0164h Capture/compare control 0 TACCTL0 0162h Timer_A control TACTL 0160h Timer_A interrupt vector TAIV 012Eh Sum extend SUMEXT 013Eh Result high word RESHI 013Ch Result low word RESLO 013Ah Second operand OP2 013
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 peripheral file map (continued) PERIPHERAL FILE MAP (CONTINUED) Comparator_A p _ Comparator_A port disable CAPD 05Bh Comparator_A control2 CACTL2 05Ah Comparator_A control1 CACTL1 059h Basic clock system control2 BCSCTL2 058h Basic clock system control1 BCSCTL1 057h DCO clock frequency control DCOCTL 056h BrownOUT, SVS SVS control register (reset by brownout signal) SVSCTL 055
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V Voltage applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC + 0.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) MSP430F15x/16x supply current into AVCC + DVCC excluding external current (AVCC = DVCC = VCC) PARAMETER I(AM) I(LPM0) I(LPM2) TEST CONDITIONS Active mode, (see Note 1) f(MCLK) = f(SMCLK) = 1 MHz, f(ACLK) = 32,768 Hz XTS=0, SELM=(0,1) 40°C to 85°C TA = −40°C Active mode, (see Note 1) f(MCLK) =
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) MSP430F161x supply current into AVCC + DVCC excluding external current (AVCC = DVCC = VCC) PARAMETER I(AM) I(LPM0) I(LPM2) TEST CONDITIONS Active mode, (see Note 1) f(MCLK) = f(SMCLK) = 1 MHz, f(ACLK) = 32,768 Hz XTS=0, SELM=(0,1) 40°C to 85°C TA = −40°C Active mode, (see Note 1) f(MCLK) = f(S
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) Schmitt-trigger inputs − ports P1, P2, P3, P4, P5, P6, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI) PARAMETER VIT+ Positive going input threshold voltage Positive-going VIT− Negative going input threshold voltage Negative-going Vhys Input voltage hysteresis (VIT+ − VIT−) VCC MIN TY
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) outputs − ports P1, P2, P3, P4, P5, P6 PARAMETER VOH VOL High level output voltage High-level Low level output voltage Low-level TEST CONDITIONS MIN TYP MAX IOH(max) = −1.5 mA, VCC = 2.2 V, See Note 1 VCC−0.25 VCC IOH(max) = −6 mA, VCC = 2.2 V, See Note 2 VCC−0.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) outputs − ports P1, P2, P3, P4, P5, P6 (continued) TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 40 TA = 25°C VCC = 2.2 V P3.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) wake-up LPM3 PARAMETER t(LPM3) TEST CONDITIONS MIN TYP VCC = 2.2 V/3 V, fDCO ≥ fDCO43 Delay time MAX 6 UNIT μs RAM PARAMETER VRAMh TEST CONDITIONS See Note 1 CPU HALTED MIN TYP MAX 1.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 650 650 VCC = 2.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) POR/brownout reset (BOR) (see Notes 1 and 2) PARAMETER TEST CONDITIONS MIN TYP td(BOR) VCC(Start) dVCC/dt ≤ 3 V/s (see Figure 10) V(B_IT−) dVCC/dt ≤ 3 V/s (see Figure 10 through Figure 12) Vhys(B_IT−) Brownout t(reset) MAX UNIT 2000 μs 0.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 typical characteristics (continued) VCC 3V 2 VCC(min)− V Vcc = 3 V typical conditions t pw 1.5 1 VCC(min) 0.5 0 0.001 1 1000 1 ns tpw − Pulse Width − μs 1 ns tpw − Pulse Width − μs Figure 11. VCC(min) Level With a Square Voltage Drop to Generate a POR/Brownout Signal VCC VCC(min)− V 2 1.5 t pw 3V Vcc = 3 V typical conditions 1 VCC(min) 0.5 0 0.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) SVS (supply voltage supervisor/monitor) PARAMETER t(SVSR) TEST CONDITIONS MIN dVCC/dt > 30 V/ms (see Figure 13) MAX 150 dVCC/dt ≤ 30 V/ms 2000 td(SVSon) SVSON, switch from VLD = 0 to VLD ≠ 0, VCC = 3 V tsettle VLD ≠ 0‡ V(SVSstart) VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 13) 150 1.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 typical characteristics Software sets VLD >0: SVS is active AVCC V(SVS_IT−) V(SVSstart) Vhys(SVS_IT−) Vhys(B_IT−) V(B_IT−) VCC(start) Brownout Brownout Region Brownout Region 1 0 SVS out td(BOR) t d(BOR) SVS Circuit is Active From VLD > to VCC < V(B_IT−) 1 0 td(SVSon) Set POR 1 td(SVSR) undefined 0 Figure 13.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) DCO (see Note 1) PARAMETER TEST CONDITIONS VCC f(DCO03) Rsel = 0 0, DCO = 3 3, MOD = 0 0, DCOR = 0 0, TA = 25°C f(DCO13) Rsel = 1 1, DCO = 3 3, MOD = 0 0, DCOR = 0 0, TA = 25°C f(DCO23) Rsel = 2 2, DCO = 3 3, MOD = 0 0, DCOR = 0 0, TA = 25°C f(DCO33) Rsel = 3 3, DCO = 3 3, MOD =
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) main DCO characteristics D Individual devices have a minimum and maximum operation frequency. The specified parameters for f(DCOx0) to f(DCOx7) are valid for all devices. D All ranges selected by Rsel(n) overlap with Rsel(n+1): Rsel0 overlaps Rsel1, ... Rsel6 overlaps Rsel7.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, power supply and input range conditions (see Note 1) PARAMETER TEST CONDITIONS MIN AVCC Analog supply voltage AVCC and DVCC are connected together AVSS and DVSS are connected together V(AVSS) = V(DVSS) = 0 V V(P6.x/Ax) Analog input voltage range (see Note 2) All P6.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, built-in reference PARAMETER Positive built in reference built-in voltage output VREF+ AVCC(min) AVCC minimum voltage, Positive built-in built in reference active IVREF+ Load current out of VREF+ terminal Load current regulation Load-current VREF+ terminal IL(VREF)+ †
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 DVCC From Power Supply + − 10 μ F DVSS 100 nF AVCC + − 10 μ F Apply External Reference [VeREF+] or Use Internal Reference [VREF+] AVSS 100 nF VREF+ or VeREF+ + − Apply External Reference 10 μ F 100 nF VREF−/VeREF− + − 10 μ F MSP430F15x MSP430F16x MSP430F161x 100 nF Figure 17.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, timing parameters PARAMETER TEST CONDITIONS fADC12CLK fADC12OSC tCONVERT Internal ADC12 oscillator Conversion time MIN TYP MAX UNIT For specified performance of ADC12 linearity parameters 2.2V/3 V 0.45 5 6.3 MHz ADC12DIV=0, fADC12CLK=fADC12OSC 2.2 V/ 3 V 3.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, temperature sensor and built-in VMID TEST CONDITIONS PARAMETER MIN TYP MAX Operating supply current into AVCC terminal (see Note 1) REFON = 0, INCH = 0Ah, ADC12ON=NA, TA = 25_C 2.2 V 40 120 ISENSOR 3V 60 160 VSENSOR† ADC12ON = 1, INCH = 0Ah, TA = 0°C 2.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit DAC, linearity specifications (see Figure 19) PARAMETER TEST CONDITIONS Resolution INL DNL EO MIN (12-bit Monotonic) Integral nonlinearity (see Note 1) Differential nonlinearity (see Note 1) Offset voltage w/o calibration (see Notes 1, 2) Offset voltage with calibration
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit DAC, linearity specifications (continued) TYPICAL INL ERROR vs DIGITAL INPUT DATA INL − Integral Nonlinearity Error − LSB 4 VCC = 2.2 V, VREF = 1.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit DAC, output specifications PARAMETER TEST CONDITIONS VCC No Load, VeREF+ = AVCC, DAC12_xDAT = 0h, DAC12IR = 1, DAC12AMPx = 7 VO Output voltage range (see Note 1, Figure 22) CL(DAC12) Max DAC12 load capacitance IL(DAC12) Max DAC12 load current RO/P(DAC12) MIN 2.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) 12-bit DAC, reference input specifications PARAMETER TEST CONDITIONS Reference input voltage range VeREF+ Ri(VREF+), Ri(VeREF+) NOTES: 1. 2. 3. 4. 5. Reference input p i t resistance VCC MIN TYP MAX DAC12IR=0 (see Notes 1 and 2) 2.2V/3V AVCC/3 AVCC+0.2 DAC12IR=1 (see Notes 3 and 4) 2.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) Conversion 1 Conversion 2 Conversion 3 VOUT 90% 90% 10% 10% tSRLH tSRHL Figure 24. Slew Rate Testing 12-bit DAC, dynamic specifications continued (TA = 25°C unless otherwise noted) PARAMETER BW−3dB TEST CONDITIONS 3-dB bandwidth, VDC=1.5V, VAC=0.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) flash memory TEST CONDITIONS PARAMETER VCC MIN TYP MAX UNIT VCC(PGM/ ERASE) Program and erase supply voltage 2.7 3.6 V fFTG Flash timing generator frequency 257 476 kHz IPGM Supply current from DVCC during program 2.7 V/ 3.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 APPLICATION INFORMATION input/output schematics port P1, P1.0 to P1.7, input/output with Schmitt trigger P1SEL.x 0 P1DIR.x Direction Control From Module 1 Pad Logic P1.0/TACLK ... 0 P1OUT.x Module X OUT 1 P1.7/TA2 P1IN.x EN Module X IN D P1IRQ.x P1IE.x Q P1IFG.x EN Set Interrupt Flag Interrupt Edge Select P1IES.x P1SEL.x PnSel.x PnDIR.x Dir. CONTROL FROM MODULE PnOUT.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 APPLICATION INFORMATION input/output schematics (continued) port P2, P2.0 to P2.2, P2.6, and P2.7 input/output with Schmitt trigger P2SEL.x 0 P2DIR.x Direction Control From Module 0: Input 1: Output 1 0 P2OUT.x Module X OUT 1 P2.0/ACLK P2.1/TAINCLK P2.2/CAOUT/TA0 Pad Logic P2.6/ADC12CLK/DMAE0 P2.7/TA0 P2IN.x EN Module X IN P2IRQ.x Bus Keeper D P2IE.x P2IFG.x EN Q CAPD.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 APPLICATION INFORMATION input/output schematics (continued) port P2, P2.3 to P2.4, input/output with Schmitt trigger P2SEL.3 0: Input 1: Output 0 P2DIR.3 Direction Control From Module 1 Pad Logic P2.3/CA0/TA1 0 P2OUT.3 Module X OUT 1 P2IN.3 EN Module X IN Bus Keeper D P2IRQ.3 P2IE.3 P2IFG.3 EN Set Q Interrupt Flag Interrupt Edge Select CAPD.3 Comparator_A CAEX P2CA P2IES.3 P2SEL.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 APPLICATION INFORMATION input/output schematics (continued) port P2, P2.5, input/output with Schmitt trigger and Rosc function for the basic clock module 0: Input 1: Output P2SEL.5 0 P2DIR.5 Direction Control From Module Pad Logic 1 P2.5/Rosc 0 P2OUT.5 Module X OUT 1 Bus Keeper P2IN.5 EN Module X IN P2IRQ.5 D P2IE.5 Q P2IFG.5 EN Set Interrupt Flag VCC Edge Select Interrupt P2IES.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 APPLICATION INFORMATION input/output schematics (continued) port P3, P3.0 and P3.4 to P3.7, input/output with Schmitt trigger P3SEL.x 0: Input 1: Output 0 P3DIR.x Direction Control From Module 1 Pad Logic P3OUT.x Module X OUT 0 P3.0/STE0 1 P3.4/UTXD0 P3.5/URXD0 P3.6/UTXD1‡ P3.7/URXD1¶ P3IN.x EN D Module X IN x: Bit Identifier, 0 and 4 to 7 for Port P3 PnSel.x PnDIR.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 APPLICATION INFORMATION input/output schematics (continued) port P3, P3.1, input/output with Schmitt trigger P3SEL.1 SYNC MM STC STE 0 P3DIR.1 0: Input 1: Output 1 DCM_SIMO Pad Logic P3.1/SIMO0/SDA 0 P3OUT1 (SI)MO0 or SDAo/p From USART0 1 P3IN.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 APPLICATION INFORMATION input/output schematics (continued) port P3, P3.2, input/output with Schmitt trigger P3SEL.2 SYNC MM STC STE 0 P3DIR.2 0: Input 1: Output 1 DCM_SOMI Pad Logic P3.2/SOMI0 0 P3OUT.2 SO(MI)0 From USART0 1 P3IN.2 EN (SO)MI0 To USART0 D port P3, P3.3, input/output with Schmitt-trigger P3SEL.3 SYNC MM STC STE 0 P3DIR.3 0: Input 1: Output 1 DCM_UCLK Pad Logic P3.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 APPLICATION INFORMATION input/output schematics (continued) port P4, P4.0 to P4.6, input/output with Schmitt trigger Module IN of pin P5.7/TBOUTH/SVSOUT P4DIR.7 P4SEL.7 P4SEL.x 0: Input 1: Output 0 P4DIR.x Direction Control From Module P4OUT.x 1 P4.0/TB0 ... 0 1 Module X OUT Bus Keeper P4.6/TB6 P4IN.x EN Module X IN D x: Bit Identifier, 0 to 6 for Port P4 PnSel.x PnDIR.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 APPLICATION INFORMATION input/output schematics (continued) port P4, P4.7, input/output with Schmitt trigger P4SEL.7 0: Input 1: Output 0 P4DIR.7 1 Pad Logic P4.7/TBCLK 0 P4OUT.7 DVSS 1 P4IN.7 EN Timer_B, D TBCLK port P5, P5.0 and P5.4 to P5.7, input/output with Schmitt trigger P5SEL.x 0: Input 1: Output 0 P5DIR.x Direction Control From Module 1 Pad Logic P5OUT.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 APPLICATION INFORMATION input/output schematics (continued) port P5, P5.1, input/output with Schmitt trigger P5SEL.1 SYNC MM 0 P5DIR.1 1 DCM_SIMO STC STE 0: Input 1: Output Pad Logic P5.1/SIMO1 0 P5OUT.1 (SI)MO1 From USART1 1 P5IN.1 EN SI(MO)1 To USART1 D port P5, P5.2, input/output with Schmitt trigger P5SEL.2 SYNC MM STC STE 0 P5DIR.2 0: Input 1: Output 1 DCM_SOMI Pad Logic P5.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 APPLICATION INFORMATION input/output schematics (continued) port P5, P5.3, input/output with Schmitt trigger P5SEL.3 SYNC MM STC STE 0 P5DIR.3 0: Input 1: Output 1 DCM_SIMO Pad Logic P5.3/UCLK1 0 P5OUT.3 UCLK1 From USART1 1 P5IN.3 EN D UCLK1 To USART1 NOTE: UART mode: The UART clock can only be an input. If UART mode and UART function are selected, the P5.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 APPLICATION INFORMATION input/output schematics (continued) port P6, P6.0 to P6.5, input/output with Schmitt trigger P6SEL.x 0 P6DIR.x Direction Control From Module 0: Input 1: Output 1 Pad Logic 0 P6OUT.x Module X OUT 1 P6.0/A0 P6.1/A1 P6.2/A2 P6.3/A3 P6.4/A4 P6.5/A5 Bus Keeper P6IN.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 APPLICATION INFORMATION input/output schematics (continued) port P6, P6.6, input/output with Schmitt trigger 0: Port Active, T-Switch Off 1: T-Switch On, Port Disabled INCH = 6† a6† ’1’, if DAC12.0AMP > 0 P6SEL.6 0: Input 1: Output 0 P6DIR.6 1 P6DIR.6 0 P6OUT.6 1 DVSS Bus Keeper P6IN.6 EN D 0, if DAC12.0CALON = 0 and DAC12.0AMP > 1 + − 1 0 1, if DAC12.0AMP >1 1, if DAC12.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 APPLICATION INFORMATION input/output schematics (continued) port P6, P6.7, input/output with Schmitt trigger To SVS Mux (15)† 0: Port Active, T-Switch Off 1: T-Switch On, Port Disabled INCH = 7‡ a7‡ ’1’, if VLD = 15§ ’1’, if DAC12.0AMP > 0 P6SEL.6 0: Input 1: Output 0 P6DIR.7 Pad Logic 1 P6DIR.7 0 P6OUT.7 1 DVSS Bus Keeper P6.7/A7/ DAC1/SVSIN P6IN.7 EN D 0, if DAC12.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 APPLICATION INFORMATION JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger TDO Controlled by JTAG Controlled by JTAG JTAG TDO/TDI Controlled by JTAG DVCC DVCC TDI Fuse Burn & Test Fuse Test TDI/TCLK and DVCC Emulation Module TMS TMS DVCC During Programming Activity and During Blowing of the Fuse, Pin TDO/TDI Is Used to Apply the Test Input Data for JTAG Circuitry TC
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 APPLICATION INFORMATION JTAG fuse check mode MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TDI/TCLK pin to ground if the fuse is not burned.
MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 Data Sheet Revision History LITERATURE NUMBER SLAS368F SLAS368G 66 SUMMARY In absolute maximum ratings table, changed Tstg min from −40°C to −55°C (page 25) Added Development Tools Support section (page 2) Changed limits on td(SVSon) parameter (page 35) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE MATERIALS INFORMATION www.ti.com 13-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant MSP430F155IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2 MSP430F156IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2 MSP430F157IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.
PACKAGE MATERIALS INFORMATION www.ti.com 13-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430F155IPMR LQFP PM 64 1000 367.0 367.0 45.0 MSP430F156IPMR LQFP PM 64 1000 367.0 367.0 45.0 MSP430F157IPMR LQFP PM 64 1000 367.0 367.0 45.0 MSP430F1610IPMR LQFP PM 64 1000 367.0 367.0 45.0 MSP430F1611IPMR LQFP PM 64 1000 367.0 367.0 45.0 MSP430F1612IPMR LQFP PM 64 1000 367.0 367.0 45.
MECHANICAL DATA MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996 PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 33 48 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040152 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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