MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 MIXED SIGNAL MICROCONTROLLER FEATURES 1 • • • • • • • • • • • • Low Supply Voltage Range 1.8 V to 3.6 V Ultra-Low Power Consumption – Active Mode: 220 µA at 1 MHz, 2.2 V – Standby Mode: 0.5 µA – Off Mode (RAM Retention): 0.1 µA Five Power-Saving Modes Ultra-Fast Wake-Up From Standby Mode in Less Than 1 µs 16-Bit RISC Architecture, 62.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com Typical applications include sensor systems that capture analog signals, convert them to digital values, and then process the data for display or for transmission to a host system. Stand alone RF sensor front end is another area of application. Table 1.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 Device Pinout, MSP430F20x1 See port schematics section for detailed I/O information. PW or N PACKAGE (TOP VIEW) VCC 1 14 VSS P1.0/TACLK/ACLK/CA0 2 13 XIN/P2.6/TA1 P1.1/TA0/CA1 3 12 XOUT/P2.7 P1.2/TA1/CA2 4 11 TEST/SBWTCK P1.3/CAOUT/CA3 5 10 P1.4/SMCLK/CA4/TCK P1.5/TA0/CA5/TMS 6 9 RST/NMI/SBWTDIO P1.7/CAOUT/CA7/TDO/TDI 7 8 P1.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com Device Pinout, MSP430F20x2 See port schematics section for detailed I/O information. PW or N PACKAGE (TOP VIEW) VCC 1 14 VSS P1.0/TACLK/ACLK/A0 2 13 XIN/P2.6/TA1 P1.1/TA0/A1 3 12 XOUT/P2.7 P1.2/TA1/A2 4 11 TEST/SBWTCK P1.3/ADC10CLK/A3/VREF−/VeREF− 5 10 P1.4/SMCLK/A4/VREF+/VeREF+/TCK P1.5/TA0/A5/SCLK/TMS 6 9 RST/NMI/SBWTDIO P1.7/A7/SDI/SDA/TDO/TDI 7 8 P1.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 Device Pinout, MSP430F20x3 See port schematics section for detailed I/O information. PW or N PACKAGE (TOP VIEW) VCC 1 14 VSS P1.0/TACLK/ACLK/A0+ 2 13 XIN/P2.6/TA1 P1.1/TA0/A0−/A4+ 3 12 XOUT/P2.7 P1.2/TA1/A1+/A4− 4 11 TEST/SBWTCK P1.3/VREF/A1− 5 10 P1.4/SMCLK/A2+/TCK P1.5/TA0/A2−/SCLK/TMS 6 9 RST/NMI/SBWTDIO P1.7/A3−/SDI/SDA/TDO/TDI 7 8 P1.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com Functional Block Diagram, MSP430F20x1 VCC VSS P1.x & JTAG 8 XIN P2.x & XIN/XOUT 2 XOUT ACLK Basic Clock System+ SMCLK MCLK Flash RAM 2kB 1kB 128B 128B Comparator _A+ 8 channel input mux Port P1 Port P2 8 I/O Interrupt capability, pull−up/down resistors 2 I/O Interrupt capability, pull−up/down resistors MAB 16MHz CPU incl.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 Functional Block Diagram, MSP430F20x3 VCC VSS P1.x & JTAG 8 XIN P2.x & XIN/XOUT 2 XOUT Basic Clock System+ ACLK SD16_A SMCLK MCLK 16MHz CPU incl.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com Table 2. Terminal Functions, MSP430F20x1 TERMINAL NAME NO. DESCRIPTION I/O PW, N RSA P1.0/TACLK/ACLK/CA0 2 1 I/O General-purpose digital I/O pin Timer_A, clock signal TACLK input ACLK signal output Comparator_A+, CA0 input P1.1/TA0/CA1 3 2 I/O General-purpose digital I/O pin Timer_A, capture: CCI0A input, compare: Out0 output Comparator_A+, CA1 input P1.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 Table 3. Terminal Functions, MSP430F20x2 TERMINAL NAME NO. DESCRIPTION I/O PW, N RSA P1.0/TACLK/ACLK/A0 2 1 I/O General-purpose digital I/O pin Timer_A, clock signal TACLK input ACLK signal output ADC10 analog input A0 P1.1/TA0/A1 3 2 I/O General-purpose digital I/O pin Timer_A, capture: CCI0A input, compare: Out0 output ADC10 analog input A1 P1.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com Table 4. Terminal Functions, MSP430F20x3 TERMINAL NAME NO. DESCRIPTION I/O PW, N RSA P1.0/TACLK/ACLK/A0+ 2 1 I/O General-purpose digital I/O pin Timer_A, clock signal TACLK input ACLK signal output SD16_A positive analog input A0 P1.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 SHORT-FORM DESCRIPTION CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com Operating Modes The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt event can wake the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 Interrupt Vector Addresses The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFC0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed) the CPU goes into LPM4 immediately after power-up. Table 7.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com Special Function Registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. Legend rw: rw-0,1: rw-(0,1): Bit can be read and written. Bit can be read and written. It is reset or set by PUC.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 Memory Organization Table 10.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com Peripherals Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, refer to the MSP430F2xx Family User's Guide.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 Timer_A2 Timer_A2 is a 16-bit timer/counter with two capture/compare registers. Timer_A2 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A2 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 12.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com Comparator_A+ (MSP430F20x1) The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions, battery-voltage supervision, and monitoring of external analog signals. USI (MSP430F20x2 and MSP430F20x3) The universal serial interface (USI) module is used for serial data communication and provides the basic hardware for synchronous communication protocols like SPI and I2C.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 Peripheral File Map Table 14.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com Absolute Maximum Ratings (1) Voltage applied at VCC to VSS -0.3 V to 4.1 V Voltage applied to any pin (2) -0.3 V to VCC + 0.3 V Diode current at any device terminal Storage temperature (3) Tstg (1) ±2 mA Unprogrammed device -55°C to 150°C Programmed device -55°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 Electrical Characteristics Active Mode Supply Current Into VCC Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) PARAMETER IAM,1MHz IAM,1MHz IAM,4kHz IAM,100kHz (1) (2) TYP MAX 2.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com Typical Characteristics - Active Mode Supply Current (Into VCC) ACTIVE MODE CURRENT vs VCC (TA = 25°C) ACTIVE MODE CURRENT vs DCO FREQUENCY 4.0 5.0 Active Mode Current − mA Active Mode Current − mA f DCO = 16 MHz 4.0 3.0 f DCO = 12 MHz 2.0 1.0 f DCO = 8 MHz TA = 25°C 2.0 TA = 85°C 1.0 2.0 2.5 TA = 25°C 3.0 VCC − Supply Voltage − V Figure 2. 22 Submit Documentation Feedback VCC = 3 V VCC = 2.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 Low-Power Mode Supply Currents (Into VCC) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER ILPM0,1MHz ILPM0,100kHz ILPM2 ILPM3,LFXT1 TEST CONDITIONS TA MAX 65 80 Low-power mode 0 (LPM0) current (3) 3V 85 100 2.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 Outputs (Ports P1 and P2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS I(OHmax) = -1.5 mA VOH (1) (2) MAX VCC - 0.25 VCC VCC - 0.6 VCC I(OHmax) = -1.5 mA (1) 3V VCC - 0.25 VCC I(OHmax) = -6 mA (2) 3V VCC - 0.6 VCC 2.2 V VSS VSS + 0.25 2.2 V VSS VSS + 0.6 I(OLmax) = 1.5 mA (1) 3V VSS VSS + 0.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com Typical Characteristics - Outputs over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 50.0 VCC = 2.2 V P1.7 TA = 25°C 25.0 TA = 85°C 20.0 15.0 10.0 5.0 0.0 0.0 0.5 1.0 1.5 2.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com Typical Characteristics - POR/Brownout Reset (BOR) VCC 3V 2 VCC(drop) − V VCC = 3 V Typical Conditions t pw 1.5 1 VCC(drop) 0.5 0 0.001 1 1000 1 ns t pw − Pulse Width − µs 1 ns t pw − Pulse Width − µs Figure 9. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal VCC 2 t pw 3V VCC(drop) − V VCC = 3 V 1.5 Typical Conditions 1 VCC(drop) 0.5 0 0.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 Main DCO Characteristics • • • All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15. DCO control bits DCOx have a step size as defined by parameter SDCO. Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com Calibrated DCO Frequencies - Tolerance at Calibration over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS Frequency tolerance at calibration TA VCC MIN TYP MAX UNIT 25°C 3V -1 ±0.2 +1 % 25°C 3V 0.990 1 1.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 Calibrated DCO Frequencies - Tolerance Over Supply Voltage VCC over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX 1-MHz tolerance over VCC 25°C 8-MHz tolerance over VCC 25°C 12-MHz tolerance over VCC 16-MHz tolerance over VCC UNIT 1.8 V to 3.6 V -3 ±2 +3 % 1.8 V to 3.6 V -3 ±2 +3 % 25°C 2.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com Typical Characteristics - Calibrated 1-MHz DCO Frequency CALIBRATED 1-MHz FREQUENCY vs TEMPERATURE CALIBRATED 1-MHz FREQUENCY vs SUPPLY VOLTAGE 1.03 1.03 1.02 1.02 Frequency − MHz 1.01 1.00 VCC = 2.2 V VCC = 3.0 V 0.99 Frequency − MHz VCC = 1.8 V 1.01 TA = 105 °C TA = 85 °C 1.00 TA = 25 °C 0.99 TA = −40 °C VCC = 3.6 V 0.98 0.98 0.97 −50.0 −25.0 0.0 25.0 50.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 Wake-Up From Lower-Power Modes (LPM3, LPM4) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ tDCO,LPM3/4 BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ DCO clock wake-up time from LPM3 or LPM4 (1) (1) (2) UNIT 2 2.2 V, 3 V 1.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 USI, Universal Serial Interface (MSP430F20x2, MSP430F20x3) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fUSI TEST CONDITIONS External: SCLK, Duty cycle = 50% ±10%, SPI slave mode USI clock frequency USI module in I2C mode, I(OLmax) = 1.5 mA VOL,I2C Low-level output voltage on SDA and SCL VCC MIN TYP MAX 2.2 V 10 3V 16 2.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com Comparator_A+ (MSP430F20x1) (1) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS I(DD) CAON = 1, CARSEL = 0, CAREF = 0 I(Refladder/RefDiode) CAON = 1, CARSEL = 0, CAREF = 1/2/3, No load at P1.0/CA0 and P1.1/CA1 VCC MIN TYP MAX 2.2 V 25 40 3V 45 60 2.2 V 30 50 3V 45 71 UNIT μA μA VIC Common-mode input voltage range CAON = 1 2.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 0V VCC 0 1 CAF CAON Low Pass Filter + _ V+ V− 0 0 1 1 To Internal Modules CAOUT Set CAIFG Flag τ ≈ 2.0 µs Figure 16. Block Diagram of Comparator_A+ Module VCAOUT Overdrive V− 400 mV t (response) V+ Figure 17. Overdrive Definition Figure 18. Comparator_A+ Short Resistance Test Condition CASHORT CA0 CA1 1 VIN + − Comparator_A+ CASHORT = 1 IOUT = 10µA Figure 19.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com Typical Characteristics, Comparator_A+ (MSP430x20x1) V(RefVT) vs TEMPERATURE (VCC = 3 V) V(RefVT) vs TEMPERATURE (VCC = 2.2 V) 650 650 VCC = 2.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com 10-Bit ADC, Built-In Voltage Reference (MSP430F20x2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC,REF+ Positive built-in reference analog supply voltage range VREF+ Positive built-in reference voltage ILD,VREF+ Maximum VREF+ load current VREF+ load regulation TEST CONDITIONS VCC MIN IVREF+ ≤ 1 mA, REF2_5V = 0 2.2 IVREF+ ≤ 0.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 10-Bit ADC, External Reference (MSP430F20x2) (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VeREF+ TEST CONDITIONS Positive external reference input voltage range (2) MIN MAX VeREF+ > VeREF-, SREF1 = 1, SREF0 = 0 1.4 VCC VeREF-≤ VeREF+ ≤ VCC - 0.15 V, SREF1 = 1, SREF0 = 1 (3) 1.4 3 0 1.2 V 1.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com 10-Bit ADC, Linearity Parameters (MSP430F20x2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT EI Integral linearity error 2.2 V, 3 V ±1 LSB ED Differential linearity error 2.2 V, 3 V ±1 LSB EO Offset error 2.2 V, 3 V ±1 LSB EG Gain error 2.2 V, 3 V ±1.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 SD16_A, Power Supply and Recommended Operating Conditions (MSP430F20x3) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER AVCC Analog supply voltage range TEST CONDITIONS TA SD16LP = 0, fSD16 = 1 MHz, SD16OSR = 256 Analog supply current including internal reference SD16 input clock frequency TYP 2.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 Typical Characteristics, SD16_A SINAD Performance Over OSR (MSP430F20x3) SINAD PERFORMANCE vs OSR (fSD16 = 1 MHz, SD16REFON = 1,SD16GAINx = 1) 90.0 85.0 SINAD − dB 80.0 75.0 70.0 65.0 RSA PW, or N 60.0 55.0 10.00 100.00 1000.00 OSR Figure 23.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com SD16_A, Built-In Voltage Reference (MSP430F20x3) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX UNIT 3V 1.14 1.20 1.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 SD16_A, Temperature Sensor (1) (MSP430F20x3) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX 1.32 1.46 mV/°C TCSensor Sensor temperature coefficient 1.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com JTAG and Spy-Bi-Wire Interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC MIN TYP MAX UNIT fSBW Spy-Bi-Wire input frequency 2.2 V, 3 V 0 20 MHz tSBW,Low Spy-Bi-Wire low clock pulse length 2.2 V, 3 V 0.025 15 µs tSBW,En Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge (1)) 2.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 APPLICATION INFORMATION, MSP430F20X1 Port P1 (P1.0 to P1.3) Pin Schematics, MSP430F20x1 Pad Logic To Comparator_A+ From Comparator_A+ CAPD.x P1REN.x P1DIR.x 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P1OUT.x DVSS DVCC P1.0/TACLK/ACLK/CA0 P1.1/TA0/CA1 P1.2/TA1/CA2 P1.3/CAOUT/CA3 Bus Keeper P1SEL.x EN P1IN.x EN Module X IN D P1IE.x P1IRQ.x EN Q Set P1IFG.x P1SEL.x P1IES.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com Table 17. Port P1 (P1.0 to P1.3) Pin Functions, MSP430F20x1 PIN NAME (P1.x) x FUNCTION P1.0 P1.0/TACLK/ACLK/CA0 0 1 0 0 1 0 ACLK 1 1 0 CA0 (3) X X 1 0/1 0 0 Timer_A2.CCI0A input/output 0 1 0 Timer_A2.TA0 1 1 0 (3) P1.2 (2) input/output 2 Timer_A2.CCI1A (1) (2) (3) 50 3 X X 1 0/1 0 0 0 1 0 Timer_A2.TA1 1 1 0 CA2 (3) X X 1 0/1 0 0 0 1 0 P1.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 Port P1 (P1.4 to P1.6) Pin Schematics, MSP430F20x1 Pad Logic To Comparator_A+ From Comparator_A+ CAPD.x P1REN.x P1DIR.x 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P1OUT.x DVSS DVCC P1.4/SMCLK/CA4/TCK P1.5/TA0/CA5/TMS P1.6/TA1/CA6/TDI Bus Keeper P1SEL.x EN P1IN.x EN Module X IN D P1IE.x P1IRQ.x EN Q Set P1IFG.x P1SEL.x P1IES.x Interrupt Edge Select To JTAG From JTAG Table 18.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com Port P1 (P1.7) Pin Schematics, MSP430F20x1 Pad Logic To Comparator_A+ From Comparator_A+ CAPD.7 P1REN.7 P1DIR.7 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P1OUT.7 DVSS P1.7/CAOUT/CA7/TDO/TDI Bus Keeper P1SEL.7 EN P1IN.7 EN Module X IN D P1IE.7 P1IRQ.7 EN Q P1IFG.7 P1SEL.7 P1IES.7 Set Interrupt Edge Select To JTAG From JTAG From JTAG From JTAG (TDO) Table 19.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 Table 20. Port P1 (P1.4 to P1.7) Pin Functions, MSP430F20x1 PIN NAME (P1.x) FUNCTION (1) x P1.4 P1.4/SMCLK/CA4/TCK 4 (3) 6 0 0 1 0 0 SMCLK 1 1 0 0 CA4 (4) X X 1 0 (5) (5) (6) X 1 0 0 0 0 1 0 0 1 1 0 0 X X 1 0 TMS (5) X X X 1 (3) 0/1 0 0 0 N/A input/output 0 1 0 0 Timer_A2.TA1 1 1 0 0 CA6 (4) X X 1 0 (5) N/A (1) (2) (3) (4) X CA5 (4) P1.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com Port P2 (P2.6) Pin Schematics, MSP430F20x1 LFXT1 Oscillator BCSCTL3.LFXT1Sx = 11 P2.7/XOUT LFXT1 off 0 LFXT1CLK 1 P2SEL.7 Pad Logic P2REN.6 P2DIR.6 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.6 DVSS P2.6/XIN/TA1 Bus Keeper P2SEL.6 EN P2IN.6 EN Module X IN D P2IE.6 P2IRQ.6 EN Q P2IFG.6 P2SEL.6 P2IES.6 Set Interrupt Edge Select Table 21. Port P2 (P2.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 Port P2 (P2.7) Pin Schematics, MSP430F20x1 LFXT1 Oscillator BCSCTL3.LFXT1Sx = 11 LFXT1 off 0 LFXT1CLK From P2.6/XIN 1 P2.6/XIN/TA1 Pad Logic P2SEL.6 P2REN.7 P2DIR.7 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.7 DVSS P2.7/XOUT Bus Keeper P2SEL.7 EN P2IN.7 EN Module X IN D P2IE.7 P2IRQ.7 EN Q Set P2IFG.7 Interrupt Edge Select P2SEL.7 P2IES.7 Table 22.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com APPLICATION INFORMATION, MSP430F20X2 Port P1 (P1.0 to P1.2) Pin Schematics, MSP430F20x2 Pad Logic To ADC 10 INCHx = x ADC10AE.x P1REN.x P1DIR.x 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P1OUT.x DVSS DVCC Bus Keeper P1SEL.x P1.0/TACLK/ACLK/A0 P1.1/TA0/A1 P1.2/TA1/A2 EN P1IN.x EN Module X IN D P1IE.x P1IRQ.x P1IFG.x P1SEL.x P1IES.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 Table 23. Port P1 (P1.0 to P1.2) Pin Functions, MSP430F20x2 PIN NAME (P1.x) x FUNCTION P1.0 P1.0/TACLK/ACLK/A0 0 1 (1) (2) (3) (4) INCHx 0 0 N/A 1 0 N/A ACLK 1 1 0 N/A A0 (4) X X 1 0 0/1 0 0 N/A Timer_A2.CCI0A input/output 0 1 0 N/A Timer_A2.TA0 1 1 0 N/A (4) P1.2 (3) input/output 2 ADC10AE.x 0 A1 P1.2/TA1/A2 P1SEL.x 0/1 (3) input/output P1DIR.x Timer_A2.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com Port P1 (P1.3) Pin Schematics, MSP430F20x2 SREF2 VSS 0 To ADC 10 VR− Pad Logic 1 A3 INCHx = 3 ADC10AE.3 P1REN.3 P1DIR.3 0 P1OUT.3 0 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 Module X OUT DVSS P1.3/ADC10CLK/ A3/VREF−/VeREF− Bus Keeper P1SEL.3 EN P1IN.3 EN Module X IN D P1IE.3 P1IRQ.3 EN Q P1IFG.3 Set Interrupt Edge Select P1SEL.3 P1IES.3 Table 24. Port P1 (P1.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 Port P1 (P1.4) Pin Schematic, MSP430F20x2 Pad Logic To /from ADC 10 positive reference A4 INCHx = 4 ADC10AE.4 P1REN.4 P1DIR.4 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P1OUT.4 DVSS DVCC P1.4/SMCLK/A4/VREF+/VeREF+/TCK Bus Keeper P1SEL.4 EN EN Module X IN D P1IE.4 P1IRQ.4 EN Q P1IFG.4 P1SEL.4 P1IES.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com Port P1 (P1.5) Pin Schematics, MSP430F20x2 Pad Logic A5 INCHx = 5 ADC10AE.5 P1REN.5 P1SEL.5 USIPE5 P1DIR.5 0 USI Module Direction 1 P1OUT.5 0 Module X OUT 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P1.5/TA0/SCLK/A5/TMS Bus Keeper EN P1IN.5 EN Module X IN D P1IE.5 P1IRQ.5 EN Q P1IFG.5 P1SEL.5 P1IES.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 Port P1 (P1.6) Pin Schematics, MSP430F20x2 Pad Logic A6 INCHx = 6 ADC10AE.6 P1REN.6 P1SEL.6 USIPE6 P1DIR.6 0 USI Module Direction 1 P1OUT.6 0 Module X OUT 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P1.6/TA1/SDO/SCL/A6/TDI USI Module Output (I2C Mode) Bus Keeper EN P1IN.6 EN Module X IN D P1IE.6 P1IRQ.6 EN Q P1IFG.6 P1SEL.6 P1IES.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com Port P1 (P1.7) Pin Schematics, MSP430F20x2 Pad Logic A7 INCHx = 7 ADC10AE.7 P1REN.7 P1SEL.7 USIPE7 P1DIR.7 0 USI Module Direction 1 P1OUT.7 0 Module X OUT 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P1.7/SDI/SDA/A7/TDO/TDI USI Module Output (I2C Mode) Bus Keeper EN P1IN.7 EN Module X IN D P1IE.7 P1IRQ.7 EN Q P1IFG.7 P1SEL.7 P1IES.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 Table 25. Port P1 (P1.4 to P1.7) Pin Functions, MSP430F20x2 PIN NAME (P1.x) x FUNCTION P1DIR.x P1SEL.x USIP.x ADC10AE.x INCHx JTAG Mode 0/1 0 N/A 0 N/A 0 N/A 0 1 N/A 0 N/A 0 SMCLK 1 1 N/A 0 N/A 0 A4 (4) X X N/A 1 4 0 VREF+/VeREF+ (4) (5) X X N/A 1 N/A 0 TCK (6) X X N/A X X 1 0/1 0 0 0 N/A 0 N/A 0 1 0 0 N/A 0 Timer_A2.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com Port P2 (P2.6) Pin Schematics, MSP430F20x2 LFXT1 Oscillator BCSCTL3.LFXT1Sx = 11 P2.7/XOUT LFXT1 off 0 LFXT1CLK 1 P2SEL.7 Pad Logic P2REN.6 P2DIR.6 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.6 DVSS P2.6/XIN/TA1 Bus Keeper P2SEL.6 EN P2IN.6 EN Module X IN D P2IE.6 P2IRQ.6 EN Q P2IFG.6 P2SEL.6 P2IES.6 Set Interrupt Edge Select Table 26. Port P2 (P2.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 Port P2 (P2.7) Pin Schematics, MSP430F20x2 LFXT1 Oscillator BCSCTL3.LFXT1Sx = 11 LFXT1 off 0 LFXT1CLK From P2.6/XIN 1 P2.6/XIN/TA1 Pad Logic P2SEL.6 P2REN.7 P2DIR.7 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.7 DVSS P2.7/XOUT Bus Keeper P2SEL.7 EN P2IN.7 EN Module X IN D P2IE.7 P2IRQ.7 EN Q Set P2IFG.7 Interrupt Edge Select P2SEL.7 P2IES.7 Table 27.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com APPLICATION INFORMATION, MSP430F20X3 Port P1 (P1.0) Pin Schematics, MSP430F20x3 INCH=0 Pad Logic A0+ SD16AE.0 P1REN.0 P1DIR.0 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P1OUT.0 DVSS P1.0/TACLK/ACLK/A0+ Bus Keeper P1SEL.0 EN P1IN.0 EN Module X IN D P1IE.0 P1IRQ.0 P1IFG.0 P1SEL.0 P1IES.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 Port P1 (P1.1) Pin Schematics, MSP430F20x3 INCH=4 Pad Logic A4+ INCH=0 0 A0− AV SS 1 SD16AE.1 P1REN.1 P1DIR.1 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P1OUT.1 DVSS P1.1/TA 0/A0−/A4+ Bus Keeper P1SEL.1 EN P1IN.1 EN Module X IN D P1IE.1 P1IRQ.1 EN Q Set P1IFG.1 P1SEL.1 P1IES.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com Port P1 (P1.2) Pin Schematics, MSP430F20x3 INCH=1 Pad Logic A1+ INCH=4 0 A4− AV SS 1 SD16AE.2 P1REN.2 P1DIR.2 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P1OUT.2 DVSS P1.2/TA 1/A1+/A4− Bus Keeper P1SEL.2 EN P1IN.2 EN Module X IN D P1IE.2 P1IRQ.2 P1IFG.2 P1SEL.2 P1IES.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 Port P1 (P1.3) Pin Schematics, MSP430F20x3 Pad Logic VREF INCH=1 0 A1− AV SS 1 SD16AE.3 P1REN.3 P1DIR.3 0 0 1 1 Direction 0: Input 1: Output 1 P1OUT.3 DVSS DVCC 0 1 P1.3/VREF/A1− Bus Keeper P1SEL.3 EN P1IN.3 P1IE.3 P1IRQ.3 EN Q P1IFG.3 P1SEL.3 P1IES.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com Table 28. Port P1 (P1.0 to P1.3) Pin Functions, MSP430F20x3 PIN NAME (P1.x) x FUNCTION P1.0 P1.0/TACLK/ACLK/A0+ 0 1 0 N/A 1 0 N/A ACLK 1 1 0 N/A A0+ (4) X X 1 0 0/1 0 0 N/A Timer_A2.CCI0A input/output 0 1 0 N/A Timer_A2.TA0 1 1 0 N/A X X 1 0 X X 1 4 0/1 0 0 N/A Timer_A2.CCI1A 0 1 0 N/A Timer_A2.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 Port P1 (P1.4) Pin Schematics, MSP430F20x3 INCH=2 Pad Logic A2+ SD16AE.4 P1REN.4 P1DIR.4 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P1OUT.4 DVSS DVCC P1.4/SMCLK/A2+/TCK Bus Keeper P1SEL.4 EN P1IN.4 EN Module X IN D P1IE.4 P1IRQ.4 EN Q P1IFG.4 P1SEL.4 P1IES.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com Port P1 (P1.5) Pin Schematics, MSP430F20x3 Pad Logic INCH=2 0 A2− AV SS 1 SD16AE.5 P1REN.5 P1SEL.5 USIPE5 P1DIR.5 0 USI Module Direction 1 P1OUT.5 0 Module X OUT 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P1.5/TA 0/SCLK/A2−/TMS Bus Keeper EN P1IN.5 EN Module X IN D P1IE.5 P1IRQ.5 EN Q P1IFG.5 P1SEL.5 P1IES.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 Port P1 (P1.6) Pin Schematics, MSP430F20x3 Pad Logic INCH=3 A3+ SD16AE.6 P1REN.6 P1SEL.6 USIPE6 P1DIR.6 0 USI Module Direction 1 P1OUT.6 0 Module X OUT 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P1.6/TA1/SDO/SCL/A3+/TDI USI Module Output (I2C Mode) Bus Keeper EN P1IN.6 EN Module X IN D P1IE.6 P1IRQ.6 EN Q P1IFG.6 P1SEL.6 P1IES.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com Port P1 (P1.7) Pin Schematics, MSP430F20x3 Pad Logic INCH=3 0 A3− AV SS 1 SD16AE.x P1REN.x P1SEL.x USIPE7 P1DIR.x 0 USI Module Direction 1 P1OUT.x 0 Module X OUT 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P1.7/SDI/SDA/A3−/TDO/TDI USI Module Output (I2C Mode) Bus Keeper EN P1IN.x EN Module X IN D P1IE.x P1IRQ.x EN Q P1IFG.x P1SEL.x P1IES.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 Table 29. Port P1 (P1.4 to P1.7) Pin Functions, MSP430F20x3 PIN NAME (P1.x) x FUNCTION P1DIR.x P1SEL.x USIP.x SD16AE.x INCHx JTAG Mode 0/1 0 N/A 0 N/A 0 N/A 0 1 N/A 0 N/A 0 SMCLK 1 1 N/A 0 N/A 0 A2+ (4) X X N/A 1 2 0 TCK (5) X X N/A X X 1 0/1 0 0 0 N/A 0 N/A 0 1 0 0 N/A 0 Timer_A2.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com Port P2 (P2.6) Pin Schematics, MSP430F20x3 LFXT1 Oscillator BCSCTL3.LFXT1Sx = 11 P2.7/XOUT LFXT1 off 0 LFXT1CLK 1 P2SEL.7 Pad Logic P2REN.6 P2DIR.6 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.6 DVSS P2.6/XIN/TA1 Bus Keeper P2SEL.6 EN P2IN.6 EN Module X IN D P2IE.6 P2IRQ.6 EN Q P2IFG.6 P2SEL.6 P2IES.6 Set Interrupt Edge Select Table 30. Port P2 (P2.
MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 Port P2 (P2.7) Pin Schematics, MSP430F20x3 LFXT1 Oscillator BCSCTL3.LFXT1Sx = 11 LFXT1 off 0 LFXT1CLK From P2.6/XIN 1 P2.6/XIN/TA1 Pad Logic P2SEL.6 P2REN.7 P2DIR.7 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.7 DVSS P2.7/XOUT Bus Keeper P2SEL.7 EN P2IN.7 EN Module X IN D P2IE.7 P2IRQ.7 EN Q Set P2IFG.7 Interrupt Edge Select P2SEL.7 P2IES.7 Table 31.
MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491I – AUGUST 2005 – REVISED DECEMBER 2012 www.ti.com REVISION HISTORY LITERATURE NUMBER SLAS491 78 SUMMARY Preliminary PRODUCT PREVIEW data sheet release SLAS491A Production data sheet release for MSP430F20x3I. Updated specification and added characterization graphs. SLAS491B Production data sheet release for MSP430F20x3T, MSP430F20x1I and MSP430F20x1T. 105°C characterization results added. SD16_A SINAD characterization results for MSP430F20x3.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant MSP430F2001IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2001IRSAR QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2001IRSAT QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.
PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant MSP430F2003TPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2003TPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2003TRSAR QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2003TRSAT QFN RSA 16 250 180.0 12.4 4.25 4.25 1.
PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430F2001IPWR MSP430F2001IRSAR TSSOP PW 14 2000 367.0 367.0 35.0 QFN RSA 16 3000 367.0 367.0 35.0 MSP430F2001IRSAT QFN RSA 16 250 210.0 185.0 35.0 MSP430F2001TPWR TSSOP PW 14 2000 367.0 367.0 35.0 MSP430F2001TRSAR QFN RSA 16 3000 367.0 367.0 35.0 MSP430F2001TRSAT QFN RSA 16 250 210.0 185.
PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430F2003TRSAR QFN RSA 16 3000 367.0 367.0 35.0 MSP430F2003TRSAT QFN RSA 16 250 210.0 185.0 35.0 MSP430F2011IPWR TSSOP PW 14 2000 367.0 367.0 35.0 MSP430F2011IPWR TSSOP PW 14 2000 367.0 367.0 35.0 MSP430F2011IRSAR QFN RSA 16 3000 367.0 367.0 35.0 MSP430F2011IRSAT QFN RSA 16 250 210.0 185.0 35.
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