SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 D Low Supply Voltage Range 1.8 V to 3.6 V D Ultralow-Power Consumption D D D D D D D D D − Active Mode: 220 µA at 1 MHz, 2.2 V − Standby Mode: 0.5 µA − Off Mode (RAM Retention): 0.1 µA Five Power-Saving Modes Ultrafast Wake-Up From Standby Mode in less than 1 µs 16-Bit RISC Architecture, 62.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 AVAILABLE OPTIONS PACKAGED DEVICES PLASTIC 14-PIN TSSOP (PW) PLASTIC 14-PIN DIP† (N) PLASTIC 16-PIN QFN (RSA) MSP430F2001IPW† MSP430F2011IPW† MSP430F2002IPW† MSP430F2012IPW† MSP430F2003IPW MSP430F2013IPW MSP430F2001IN† MSP430F2011IN† MSP430F2002IN† MSP430F2012IN† MSP430F2003IN† MSP430F2013IN† MSP430F2001IRSA† MSP430F2011IRSA† MSP430F2002IRSA† MSP430F2012IRSA† MSP430F2003IRSA† MSP430F2013IRSA† T
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 device pinout, MSP430x20x2 PW or N PACKAGE (TOP VIEW) VCC P1.0/TACLK/ACLK/A0 1 14 2 13 VSS XIN/P2.6/TA1 P1.1/TA0/A1 3 12 XOUT/P2.7 P1.2/TA1/A2 4 11 TEST/SBWTCK P1.3/ADC10CLK/A3/VREF−/VeREF− 5 10 P1.4/SMCLK/A4/VREF+/VeREF+/TCK P1.5/TA0/A5/SCLK/TMS 6 9 RST/NMI/SBWTDIO P1.7/A7/SDI/SDA/TDO/TDI 7 8 P1.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 device pinout, MSP430x20x3 PW or N PACKAGE (TOP VIEW) VCC P1.0/TACLK/ACLK/A0+ 1 14 2 13 VSS XIN/P2.6/TA1 P1.1/TA0/A0−/A4+ 3 12 XOUT/P2.7 P1.2/TA1/A1+/A4− 4 11 TEST/SBWTCK P1.3/VREF/A1− 5 10 P1.4/SMCLK/A2+/TCK P1.5/TA0/A2−/SCLK/TMS 6 9 RST/NMI/SBWTDIO P1.7/A3−/SDI/SDA/TDO/TDI 7 8 P1.6/TA1/A3+/SDO/SCL/TDI/TCLK AVSS DVSS 15 14 11 XOUT/P2.7 P1.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 functional block diagram, MSP430x20x1 VCC VSS P1.x & JTAG 8 P2.x & XIN/XOUT 2 XOUT XIN Basic Clock System+ ACLK SMCLK MCLK Flash RAM 2kB 1kB 128B 128B Comparator _A+ 8 channel input mux Port P1 Port P2 8 I/O Interrupt capability, pull−up/down resistors 2 I/O Interrupt capability, pull−up/down resistors MAB 16MHz CPU incl.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 functional block diagram, MSP430x20x3 VCC VSS P1.x & JTAG 8 XOUT XIN Basic Clock System+ 16MHz CPU incl.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 Terminal Functions, MSP430x20x1 TERMINAL PW, or N RSA NO. NO. P1.0/TACLK/ACLK/CA0 2 1 I/O General-purpose digital I/O pin Timer_A, clock signal TACLK input ACLK signal ouput Comparator_A+, CA0 input P1.1/TA0/CA1 3 2 I/O General-purpose digital I/O pin Timer_A, capture: CCI0A input, compare: Out0 output Comparator_A+, CA1 input P1.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 Terminal Functions, MSP430x20x2 TERMINAL PW, or N RSA NO. NO. P1.0/TACLK/ACLK/A0 2 1 I/O General-purpose digital I/O pin Timer_A, clock signal TACLK input ACLK signal ouput ADC10 analog input A0 P1.1/TA0/A1 3 2 I/O General-purpose digital I/O pin Timer_A, capture: CCI0A input, compare: Out0 output ADC10 analog input A1 P1.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 Terminal Functions, MSP430x20x2 (Continued) TERMINAL PW, or N RSA NO. NO. DVCC NA 16 Digital supply voltage AVCC DVSS NA 15 Analog supply voltage NA 14 Digital ground reference AVSS QFN Pad NA 13 NA Package Pad NAME DESCRIPTION I/O Analog ground reference NA QFN package pad connection to VSS recommended. † TDO or TDI is selected via JTAG instruction. NOTE: If XOUT/P2.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 Terminal Functions, MSP430x20x3 (Continued) TERMINAL PW, or N RSA NO. NO. XIN/P2.6/TA1 13 12 I/O Input terminal of crystal oscillator General-purpose digital I/O pin Timer_A, compare: Out1 output XOUT/P2.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 short-form description CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 operating modes The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 interrupt vector addresses The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh−0FFC0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g. flash is not programmed) the CPU will go into LPM4 immediately after power-up.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 special function registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 memory organization MSP430F200x MSP430F201x Memory Main: interrupt vector Main: code memory Size Flash Flash 1KB Flash 0FFFFh−0FFC0h 0FFFFh−0FC00h 2KB Flash 0FFFFh−0FFC0h 0FFFFh−0F800h Information memory Size Flash 256 Byte 010FFh − 01000h 256 Byte 010FFh − 01000h Size 128 Byte 027Fh − 0200h 128 Byte 027Fh − 0200h 16-bit 8-bit 8-bit SFR 01FFh − 0100h 0FFh − 010h 0Fh − 00h 01FFh − 0100h
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 peripherals Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, refer to the MSP430x2xx Family User’s Guide.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 timer_A2 Timer_A2 is a 16-bit timer/counter with two capture/compare registers. Timer_A2 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A2 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 USI (MSP430x20x2 and MSP430x20x3 only) The universal serial interface (USI) module is used for serial data communication and provides the basic hardware for synchronous communication protocols like SPI and I2C. ADC10 (MSP430x20x2 only) The ADC10 module supports fast, 10-bit analog-to-digital conversions.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 peripheral file map PERIPHERALS WITH WORD ACCESS ADC10 (MSP430x20x2 only) ADC control 0 ADC control 1 ADC memory ADC10CTL0 ADC10CTL0 ADC10MEM 01B0h 01B2h 01B4h SD16_A (MSP430x20x3 only) General Control Channel 0 Control Interrupt vector word register Channel 0 conversion memory SD16CTL SD16CCTL0 SD16IV SD16MEM0 0100h 0102h 0110h 0112h Timer_A Capture/compare register Capture/compare register
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 absolute maximum ratings† Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V Voltage applied to any pin (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC+0.3 V Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . .
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) active mode supply current (into VCC) excluding external current (see Notes 1 and 2) PARAMETER IAM, 1MHz IAM, 1MHz IAM, 4kHz IAM,100kHz TEST CONDITIONS Active mode (AM) current (1MHz) Active mode (AM) current (1MHz) Active mode (AM) current (4kHz) Active mode (AM)
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) low power mode supply currents (into VCC) excluding external current (see Notes 1 and 2) PARAMETER TEST CONDITIONS VCC Low-power mode 0 (LPM0) current, see Note 3 fMCLK = 0MHz, fSMCLK = fDCO = 1MHz, fACLK = 32,768Hz, BCSCTL1 = CALBC1_1MHz, DCOCTL = CALDCO_1M
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) Schmitt-trigger inputs − Ports P1 and P2 PARAMETER VIT+ VIT− TEST CONDITIONS Positive-going input threshold voltage Negative-going input threshold voltage Vhys Input voltage hysteresis (VIT+ − VIT−) RPull Pull-up/pull-down resistor For pull-up: VIN = V
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) outputs − Ports P1 and P2 PARAMETER VOH VOL High-level output voltage Low-level output voltage TEST CONDITIONS VCC MIN I(OHmax) = −1.5 mA (see Notes 1) I(OHmax) = −6 mA (see Notes 2) 2.2 V VCC−0.25 VCC−0.6 VCC VCC I(OHmax) = −1.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) typical characteristics − outputs TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 50.0 VCC = 2.2 V P1.7 TA = 25°C 25.0 TA = 85°C 20.0 15.0 10.0 5.0 0.0 0.0 0.5 1.0 1.5 2.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) POR/brownout reset (BOR) (see Notes 1 and 2) PARAMETER TEST CONDITIONS VCC(start) (see Figure 8) dVCC/dt ≤ 3 V/s V(B_IT−) Vhys(B_IT−) (see Figure 8 through Figure 10) dVCC/dt ≤ 3 V/s dVCC/dt ≤ 3 V/s td(BOR) (see Figure 8) t(reset) Pulse length needed
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) typical characteristics − POR/brownout reset (BOR) VCC 3V 2 VCC(drop) − V VCC = 3 V Typical Conditions t pw 1.5 1 VCC(drop) 0.5 0 0.001 1 1000 1 ns tpw − Pulse Width − µs 1 ns tpw − Pulse Width − µs Figure 9.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) main DCO characteristics D All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15. D DCO control bits DCOx have a step size as defined by parameter SDCO.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) calibrated DCO frequencies − tolerance at calibration PARAMETER TEST CONDITIONS Frequency tolerance at calibration TA 25°C VCC MIN TYP MAX UNIT 3V −1 ±0.2 +1 25°C 3V 0.990 1 1.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) calibrated DCO frequencies − tolerance over supply voltage VCC PARAMETER TEST CONDITIONS 1 MHz tolerance over VCC TA 25°C VCC MIN TYP MAX UNIT 1.8 V − 3.6 V −2.5 ±2 +2.5 % 8 MHz tolerance over VCC 25°C 1.8 V − 3.6 V −2.5 ±2 +2.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) typical characteristics − calibrated 1MHz DCO frequency 1.03 1.02 VCC = 1.8 V Frequency − MHz 1.01 VCC = 2.2 V 1.00 VCC = 3.0 V 0.99 VCC = 3.6 V 0.98 0.97 −50.0 −25.0 0.0 25.0 50.0 75.0 100.0 TA − Temperature − °C Figure 11.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) wake-up from lower power modes (LPM3/4) PARAMETER TEST CONDITIONS DCO clock wake-up time from tDCO,LPM3/4 LPM3/4 (see Note 1) VCC MIN TYP MAX BCSCTL1= CALBC1_1MHz; DCOCTL = CALDCO_1MHz 2.2 V/3 V 2 BCSCTL1= CALBC1_8MHz; DCOCTL = CALDCO_8MHz 2.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) crystal oscillator, LFXT1, low frequency modes (see Note 4) PARAMETER fLFXT1,LF LFXT1 oscillator crystal frequency, LF mode 0, 1 LFXT1 oscillator logic level fLFXT1,LF,logic square wave input frequency, LF mode OALF CL,eff Oscillation Allowance for LF cryst
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) Timer_A PARAMETER TEST CONDITIONS fTA Timer_A clock frequency tTA,cap Timer_A, capture timing VCC Internal: SMCLK, ACLK; External: TACLK, INCLK; Duty Cycle = 50% ±10% MIN TYP MAX 2.2 V 10 3V 16 UNIT MHz TA0, TA1 2.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 MSP430x20x1 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) Comparator_A+ (see Note 1, MSP430x20x1 only) PARAMETER TEST CONDITIONS I(DD) CAON=1, CARSEL=0, CAREF=0 I(Refladder/RefDiode) CAON=1, CARSEL=0, CAREF=1/2/3, no load at P1.0/CA0 and P1.1/CA1 V(IC) V(Ref025) V(Ref050) Common-mode input voltage Voltage @ 0.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 MSP430x20x1 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) 0 V VCC 0 1 CAF CAON To Internal Modules Low Pass Filter + _ V+ V− 0 0 1 1 CAOUT Set CAIFG Flag τ ≈ 2.0 µs Figure 16. Block Diagram of Comparator_A+ Module VCAOUT Overdrive V− 400 mV t(response) V+ Figure 17.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 MSP430x20x1 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) typical characteristics − Comparator_A+ (MSP430x20x1 only) 650 650 VCC = 2.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 MSP430x20x2 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) 10-bit ADC, power supply and input range conditions (see Note 1, MSP430x20x2 only) PARAMETER TEST CONDITIONS VCC TYP MAX VCC Analog supply voltage range VAx Analog input voltage range (see Note 2) fADC10CLK = 5.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 MSP430x20x2 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) 10-bit ADC, built-in voltage reference (MSP430x20x2 only) PARAMETER VCC,REF+ TEST CONDITIONS Positive built-in reference analog supply voltage range VREF+ Positive built-in reference voltage ILD,VREF+ Maximum VREF+ load current VCC IVREF+ ≤
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 MSP430x20x2 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) 10-bit ADC, external reference (see Note 1, MSP430x20x2 only) PARAMETER VeREF+ TEST CONDITIONS Positive external reference input voltage range (see Note 2) TYP MAX UNIT 1.4 VCC V VeREF− ≤ VeREF+ ≤ VCC − 0.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 MSP430x20x2 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) 10-bit ADC, timing parameters (MSP430x20x2 only) PARAMETER fADC10CLK fADC10OSC tCONVERT TEST CONDITIONS For specified performance of ADC10 linearity parameters ADC10 input clock frequency ADC10 built-in oscillator frequency Conversion time VC
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 MSP430x20x2 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) 10-bit ADC, temperature sensor and built-in VMID (MSP430x20x2 only) PARAMETER ISENSOR Temperature sensor supply current (see Note 1) TEST CONDITIONS REFON = 0, INCHx = 0Ah, TA = 25_C TCSENSOR† ADC10ON = 1, INCHx = 0Ah (see Notes 2, 3) VOffset,Se
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 MSP430x20x3 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) SD16_A, power supply and recommended operating conditions (MSP430x20x3 only) PARAMETER AVCC ISD16 fSD16 TEST CONDITIONS VCC AVCC = DVCC = VCC AVSS = DVSS = VSS = 0V Analog supply voltage range Analog supply current including internal reference SD16 input
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 MSP430x20x3 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) SD16_A, SINAD performance (fSD16 = 1MHz, SD16OSRx = 1024, SD16REFON = 1, MSP430x20x3 only) PW, or N PARAMETER TEST CONDITIONS SD16GAINx = 1, Signal Amplitude: VIN = 500mV, Signal Frequency: fIN = 100Hz SD16GAINx = 2, Signal Amplitude: VIN = 250mV, S
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 MSP430x20x3 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) typical characteristics − SD16_A SINAD performance over OSR (MSP430x20x3 only) 100.0 95.0 90.0 SINAD − dB 85.0 80.0 75.0 70.0 65.0 60.0 PW, or N 55.0 50.0 10.00 100.00 1000.00 OSR Figure 22.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 MSP430x20x3 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) SD16_A, temperature sensor (MSP430x20x3 only) PARAMETER TEST CONDITIONS TCSensor Sensor temperature coefficient VOffset,Sensor Sensor offset voltage VSensor Sensor output voltage (see Note 3) VCC MIN See Note 1 1.18 See Note 1 −100 TYP 1.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) Flash Memory PARAMETER VCC(PGM/ ERASE) TEST CONDITIONS VCC Program and Erase supply voltage MIN TYP 2.2 fFTG IPGM Flash Timing Generator frequency Supply current from VCC during program 2.2 V/3.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) JTAG and Spy-Bi-Wire Interface TEST CONDITIONS PARAMETER fSBW tSBW,Low VCC MIN TYP MAX UNIT Spy-Bi-Wire input frequency 2.2 V / 3 V 0 20 MHz Spy-Bi-Wire low clock pulse length 2.2 V / 3 V 0.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 APPLICATION INFORMATION, MSP430x20x1 Port P1 (P1.0 to P1.3) pin functions, MSP430x20x1 PIN NAME (P1.X) P1.0/TACLK/ACLK/ CA0 P1.1/TA0/CA1 P1.2/TA1/CA2 CONTROL BITS / SIGNALS X FUNCTION 0 P1.0† Input/Output Timer_A2.TACLK/INCLK P1SEL.x CAPD.x 0/1 0 0 0 1 0 ACLK 1 1 0 CA0 (see Note 3) X X 1 0/1 0 0 Timer_A2.CCI0A 0 1 0 Timer_A2.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 Port P1 (P1.0 to P1.3) pin schematics, MSP430x20x1 Pad Logic To Comparator_A+ From Comparator_A+ CAPD.x P1REN.x P1DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P1OUT.x DVSS P1.0/TACLK/ACLK/CA0 P1.1/TA0/CA1 P1.2/TA1/CA2 P1.3/CAOUT/CA3 Bus Keeper P1SEL.x EN P1IN.x EN Module X IN D P1IE.x EN P1IRQ.x Q P1IFG.x P1SEL.x P1IES.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 Port P1 (P1.4 to P1.7) pin functions, MSP430x20x1 PIN NAME (P1.X) P1.4/SMCLK/CA4/ TCK CONTROL BITS / SIGNALS X FUNCTION P1DIR.x P1SEL.x CAPD.x JTAG Mode 0/1 0 0 0 N/A 0 1 0 0 SMCLK 1 1 0 0 CA4 (see Note 3) X X 1 0 4 P1.4† Input/Output TCK (see Note 4) P1.5/TA0/CA5/ TMS P1.6/TA1/CA6/ TDI P1.7/CAOUT/CA7/ TDO/TDI 5 P1.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 Port P1 (P1.4 to P1.6) pin schematics, MSP430x20x1 Pad Logic To Comparator_A+ From Comparator_A+ CAPD.x P1REN.x P1DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P1OUT.x DVSS P1.4/SMCLK/CA4/TCK P1.5/TA0/CA5/TMS P1.6/TA1/CA6/TDI Bus Keeper P1SEL.x EN P1IN.x EN Module X IN D P1IE.x P1IRQ.x EN Q P1IFG.x P1SEL.x P1IES.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 Port P1 (P1.7) pin schematics, MSP430x20x1 Pad Logic To Comparator_A+ From Comparator_A+ CAPD.7 P1REN.7 P1DIR.7 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P1OUT.7 DVSS P1.7/CAOUT/CA7/TDO/TDI Bus Keeper P1SEL.7 EN P1IN.7 EN Module X IN D P1IE.7 P1IRQ.7 EN Q P1IFG.7 P1SEL.7 P1IES.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 Port P2 (P2.6) pin schematics, MSP430x20x1 LFXT1 Oscillator BCSCTL3.LFXT1Sx = 11 P2.7/XOUT LFXT1 off 0 LFXT1CLK 1 P2SEL.7 Pad Logic P2REN.6 P2DIR.6 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.6 DVSS P2.6/XIN/TA1 Bus Keeper P2SEL.6 EN P2IN.6 EN Module X IN D P2IE.6 P2IRQ.6 EN Q P2IFG.6 P2SEL.6 P2IES.6 Set Interrupt Edge Select Port P2 (P2.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 Port P2 (P2.7) pin schematics, MSP430x20x1 LFXT1 Oscillator BCSCTL3.LFXT1Sx = 11 LFXT1 off 0 LFXT1CLK From P2.6/XIN 1 P2.6/XIN/TA1 Pad Logic P2SEL.6 P2REN.7 P2DIR.7 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.7 DVSS P2.7/XOUT Bus Keeper P2SEL.7 EN P2IN.7 EN Module X IN D P2IE.7 P2IRQ.7 EN Q P2IFG.7 Set Interrupt Edge Select P2SEL.7 P2IES.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 APPLICATION INFORMATION, MSP430x20x2 Port P1 (P1.0 to P1.2) pin functions, MSP430x20x2 PIN NAME (P1.X) P1.0/TACLK/ACLK/A0 CONTROL BITS / SIGNALS X FUNCTION 0 P1.0† Input/Output Timer_A2.TACLK/INCLK P1.1/TA0/A1 P1.2/TA1/A2 P1DIR.x P1SEL.x ADC10AE.x INCHx 0/1 0 0 N/A 0 1 0 N/A N/A ACLK 1 1 0 A0 (see Note 3) X X 1 0 1 P1.1† Input/Output 0/1 0 0 N/A Timer_A2.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 Port P1 (P1.0 to P1.2) pin schematics, MSP430x20x2 Pad Logic To ADC 10 INCHx = x ADC10AE.x P1REN.x P1DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P1OUT.x DVSS Bus Keeper P1SEL.x P1.0/TACLK/ACLK/A0 P1.1/TA0/A1 P1.2/TA1/A2 EN P1IN.x EN Module X IN D P1IE.x P1IRQ.x EN Q P1IFG.x P1SEL.x P1IES.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 Port P1 (P1.3) pin schematics, MSP430x20x2 SREF2 VSS 0 To ADC 10 VR− Pad Logic 1 A3 INCHx = 3 ADC10AE.3 P1REN.3 P1DIR.3 0 P1OUT.3 0 1 0 1 1 Direction 0: Input 1: Output 1 Module X OUT DVSS DVCC P1.3/ADC10CLK/ A3/VREF−/VeREF− Bus Keeper P1SEL.3 EN P1IN.3 EN Module X IN D P1IE.3 P1IRQ.3 EN Q P1IFG.3 Set Interrupt Edge Select P1SEL.3 P1IES.3 Port P1 (P1.0 to P1.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 Port P1 (P1.4 to P1.7) pin functions, MSP430x20x2 CONTROL BITS / SIGNALS PIN NAME (P1.X) P1.4/SMCLK/A4/ VREF+/VeREF+/ TCK X FUNCTION 4 P1.4† Input/Output N/A P1.6/TA1/SDO/SCL/A6/ TDI P1.7/SDI/SDA/A7/ TDO/TDI INCHx JTAG Mode 0 0 N/A 0 1 0 N/A 0 0 N/A 0 1 4 0 1 N/A 0 P1SEL.x 0/1 0 SMCLK 1 1 A4 (see Note 3) X X VREF+/VeREF+ (see Notes 3, 4) X X TCK (see Note 5) P1.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 Port P1 (P1.4) pin schematics, MSP430x20x2 Pad Logic To /from ADC10 positive reference A4 INCHx = 4 ADC10AE.4 P1REN.4 P1DIR.4 0 0 Module X OUT 1 0 DVCC 1 P1.4/SMCLK/A4/VREF+/VeREF+/TCK Bus Keeper P1SEL.4 EN EN Module X IN D P1IE.4 P1IRQ.4 EN Q P1IFG.4 P1SEL.4 P1IES.4 Set Interrupt Edge Select To JTAG From JTAG 60 1 Direction 0: Input 1: Output 1 P1OUT.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 Port P1 (P1.5) pin schematics, MSP430x20x2 Pad Logic A5 INCHx = 5 ADC10AE.5 P1REN.5 P1SEL.5 USIPE5 P1DIR.5 0 USI Module Direction 1 P1OUT.5 0 Module X OUT 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P1.5/TA0/SCLK/A5/TMS Bus Keeper EN P1IN.5 EN Module X IN D P1IE.5 P1IRQ.5 EN Q P1IFG.5 P1SEL.5 P1IES.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 Port P1 (P1.6) pin schematics, MSP430x20x2 Pad Logic A6 INCHx = 6 ADC10AE.6 P1REN.6 P1SEL.6 USIPE6 P1DIR.6 0 USI Module Direction 1 P1OUT.6 0 Module X OUT 1 DVSS 0 DVCC 1 Direction 0: Input 1: Output P1.6/TA1/SDO/SCL/A6/TDI USI Module Output (I2C Mode) Bus Keeper EN P1IN.6 EN Module X IN D P1IE.6 P1IRQ.6 EN Q P1IFG.6 P1SEL.6 P1IES.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 Port P1 (P1.7) pin schematics, MSP430x20x2 Pad Logic A7 INCHx = 7 ADC10AE.7 P1REN.7 P1SEL.7 USIPE7 P1DIR.7 0 USI Module Direction 1 P1OUT.7 0 Module X OUT 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P1.7/SDI/SDA/A7/TDO/TDI USI Module Output (I2C Mode) Bus Keeper EN P1IN.7 EN Module X IN D P1IE.7 P1IRQ.7 EN Q P1IFG.7 P1SEL.7 P1IES.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 Port P2 (P2.6) pin schematics, MSP430x20x2 LFXT1 Oscillator BCSCTL3.LFXT1Sx = 11 P2.7/XOUT LFXT1 off 0 LFXT1CLK 1 P2SEL.7 Pad Logic P2REN.6 P2DIR.6 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.6 DVSS P2.6/XIN/TA1 Bus Keeper P2SEL.6 EN P2IN.6 EN Module X IN D P2IE.6 P2IRQ.6 EN Q P2IFG.6 P2SEL.6 P2IES.6 Set Interrupt Edge Select Port P2 (P2.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 Port P2 (P2.7) pin schematics, MSP430x20x2 LFXT1 Oscillator BCSCTL3.LFXT1Sx = 11 LFXT1 off 0 LFXT1CLK From P2.6/XIN 1 P2.6/XIN/TA1 Pad Logic P2SEL.6 P2REN.7 P2DIR.7 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.7 DVSS P2.7/XOUT Bus Keeper P2SEL.7 EN P2IN.7 EN Module X IN D P2IE.7 P2IRQ.7 EN Q P2IFG.7 Set Interrupt Edge Select P2SEL.7 P2IES.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 APPLICATION INFORMATION, MSP430x20x3 Port P1 (P1.0 to P1.3) pin functions, MSP430x20x3 PIN NAME (P1.X) P1.0/TACLK/ACLK/A0+ CONTROL BITS / SIGNALS X FUNCTION 0 P1.0† Input/Output Timer_A2.TACLK/INCLK P1.1/TA0/A0−/A4+ SD16AE.x INCHx 0 0 N/A 0 1 0 N/A N/A 1 1 0 A0+ (see Note 3) X X 1 0 0/1 0 0 N/A Timer_A2.CCI0A 0 1 0 N/A Timer_A2.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 Port P1 (P1.0) pin schematics, MSP430x20x3 INCH=0 Pad Logic A0+ SD16AE.0 P1REN.0 P1DIR.0 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P1OUT.0 DVSS P1.0/TACLK/ACLK/A0+ Bus Keeper P1SEL.0 EN P1IN.0 EN Module X IN D P1IE.0 P1IRQ.0 EN Q Set P1IFG.0 P1SEL.0 P1IES.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 Port P1 (P1.1) pin schematics, MSP430x20x3 INCH=4 Pad Logic A4+ INCH=0 0 A0− AV SS 1 SD16AE.1 P1REN.1 P1DIR.1 0 0 Module X OUT 1 0 1 P1.1/TA0/A0−/A4+ Bus Keeper P1SEL.1 EN P1IN.1 EN Module X IN D P1IE.1 P1IRQ.1 EN Q Set P1IFG.1 P1SEL.1 P1IES.1 68 1 Direction 0: Input 1: Output 1 P1OUT.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 Port P1 (P1.2) pin schematics, MSP430x20x3 INCH=1 Pad Logic A1+ INCH=4 0 A4− AV SS 1 SD16AE.2 P1REN.2 P1DIR.2 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P1OUT.2 DVSS DVCC P1.2/TA1/A1+/A4− Bus Keeper P1SEL.2 EN P1IN.2 EN Module X IN D P1IE.2 P1IRQ.2 EN Q Set P1IFG.2 P1SEL.2 P1IES.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 Port P1 (P1.3) pin schematics, MSP430x20x3 Pad Logic VREF INCH=1 0 A1− AV SS 1 SD16AE.3 P1REN.3 P1DIR.3 0 0 1 1 Direction 0: Input 1: Output 1 P1OUT.3 DVSS DVCC 0 1 P1.3/VREF/A1− Bus Keeper P1SEL.3 EN P1IN.3 P1IE.3 P1IRQ.3 EN Q Set P1IFG.3 P1SEL.3 P1IES.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 Port P1 (P1.4 to P1.7) pin functions, MSP430x20x3 CONTROL BITS / SIGNALS PIN NAME (P1.X) P1.4/SMCLK/A2+/ TCK P1.5/TA0/SCLK/A2−/ TMS P1.6/TA1/SDO/SCL/A3+/ TDI P1.7/SDI/SDA/A3−/ TDO/TDI X FUNCTION 4 P1.4† Input/Output N/A P1DIR.x P1SEL.x USIP.x SD16AE.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 Port P1 (P1.4) pin schematics, MSP430x20x3 INCH=2 Pad Logic A2+ SD16AE.4 P1REN.4 P1DIR.4 0 0 Module X OUT 1 0 DVCC 1 P1.4/SMCLK/A2+/TCK Bus Keeper P1SEL.4 EN P1IN.4 EN Module X IN D P1IE.4 EN P1IRQ.4 Q Set P1IFG.4 P1SEL.4 P1IES.4 Interrupt Edge Select To JTAG From JTAG 72 1 Direction 0: Input 1: Output 1 P1OUT.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 Port P1 (P1.5) pin schematics, MSP430x20x3 Pad Logic INCH=2 0 A2− AV SS 1 SD16AE.5 P1REN.5 P1SEL.5 USIPE5 P1DIR.5 0 USI Module Direction 1 P1OUT.5 0 Module X OUT 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P1.5/TA0/SCLK/A2−/TMS Bus Keeper EN P1IN.5 EN Module X IN D P1IE.5 P1IRQ.5 EN Q Set P1IFG.5 P1SEL.5 P1IES.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 Port P1 (P1.6) pin schematics, MSP430x20x3 Pad Logic INCH=3 A3+ SD16AE.6 P1REN.6 P1SEL.6 USIPE6 P1DIR.6 0 USI Module Direction 1 P1OUT.6 0 Module X OUT 1 DVSS 0 DVCC 1 Direction 0: Input 1: Output P1.6/TA1/SDO/SCL/A3+/TDI USI Module Output (I2C Mode) Bus Keeper EN P1IN.6 EN Module X IN D P1IE.6 P1IRQ.6 EN Q Set P1IFG.6 P1SEL.6 P1IES.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 Port P1 (P1.7) pin schematics, MSP430x20x3 Pad Logic INCH=3 0 A3− AV SS 1 SD16AE.x P1REN.x P1SEL.x USIPE7 P1DIR.x 0 USI Module Direction 1 P1OUT.x 0 Module X OUT 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P1.7/SDI/SDA/A3−/TDO/TDI USI Module Output (I2C Mode) Bus Keeper EN P1IN.x EN Module X IN D P1IE.x P1IRQ.x EN Q Set P1IFG.x P1SEL.x P1IES.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 Port P2 (P2.6) pin schematics, MSP430x20x3 LFXT1 Oscillator BCSCTL3.LFXT1Sx = 11 P2.7/XOUT LFXT1 off 0 LFXT1CLK 1 P2SEL.7 Pad Logic P2REN.6 P2DIR.6 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.6 DVSS P2.6/XIN/TA1 Bus Keeper P2SEL.6 EN P2IN.6 EN Module X IN D P2IE.6 P2IRQ.6 EN Q P2IFG.6 P2SEL.6 P2IES.6 Set Interrupt Edge Select Port P2 (P2.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 Port P2 (P2.7) pin schematics, MSP430x20x3 LFXT1 Oscillator BCSCTL3.LFXT1Sx = 11 LFXT1 off 0 LFXT1CLK From P2.6/XIN 1 P2.6/XIN/TA1 Pad Logic P2SEL.6 P2REN.7 P2DIR.7 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.7 DVSS P2.7/XOUT Bus Keeper P2SEL.7 EN P2IN.7 EN Module X IN D P2IE.7 P2IRQ.7 EN Q P2IFG.7 Set Interrupt Edge Select P2SEL.7 P2IES.
SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005 Data Sheet Revision History Literature Number SLAS491 SLAS491A Summary Preliminary PRODUCT PREVIEW datasheet release. MSP430x20x3 production datasheet release. Updated specification and added characterization graphs. NOTE: The referring page and figure numbers are referred to the respective document revision.
MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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